Low Noise Amplifier Research Articles

A 26-28 GHz, Two-Stage, Low-Noise Amplifier for Fifth-Generation Radio Frequency and Millimeter-Wave Applications.

This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses low-voltage supply and low-current-density transistors to simultaneously achieve high gain and low noise figures (NFs). The two-stage LNA topology is analyzed and designed using 0.25 µm SiGe BiCMOS process technology from NXP semiconductors. The measured circuit shows a small signal gain at 26 GHz of 26 dB with a gain error below 1 dB on the entire frequency band (26-28 GHz). The measured average NF is 3.84 dB, demonstrated over the full frequency band under 15 mA current consumption per stage, supplied with a voltage of 3.3 V.

Robust Ku-Band GaN Low-Noise Amplifier MMIC

This paper employs the 0.2 μm ETRI GaN HEMT process on SiC to develop a Ku-band GaN low-noise amplifier monolithic microwave integrated circuit (MMIC) characterized by high-input power robustness for radar transceiver modules. A source degeneration inductor is employed to obtain the proposed amplifier’s stable operation and the compromised impedance trajectory of the maximum available gain and minimum noise figure. The analysis results show simultaneous gain and noise impedance matching, achieved using only a small number of passive elements. Furthermore, the proposed low-noise amplifier MMIC secures a linear gain of 21.3−22.6 dB, an input return loss of 19.6−21.4 dB, and a noise figure of 1.7−1.8 dB in the 15–16 GHz frequency range. It also exhibits an input 1 dB compression point of 0.4−1.5 dBm in the single-tone power test, and an input third-order intercept point of 5.8−10.1 dBm within the 15−16 GHz frequency range in the two-tone intermodulation distortion test.

A High Gain Concurrent Dual-band Low-Noise Amplifier in 130-nm BiCMOS Technology

This paper presents a fully integrated concurrent 15/30-GHz dual-band low-noise amplifier (LNA). The proposed concurrent LNA IC is designed and simulated in 130-nm BiCMOS technology. The new passive LC notch filter is proposed to realize high gain and low noise figure over dual-band frequency, simultaneously. The simulated BiCMOS LNA IC has exhibited peak gains of 30.1/23.7 dB at 15/30-GHz, respectively, with 20-mW power consumption from 1-V supply. The concurrent dual-band LNA achieves noise figure of 2.2/2.9-dB and IIP3 of -18.2/-8.8 dBm at the respective passbands. Therefore, the proposed dual band concurrent LNA IC is applicable to front-end RF receivers for Ku-Band and Ka-Band systems.

A high linearity wideband common-gate LNA with modified differential inductor

In this paper a modified derivation (MD) wideband common-gate low-noise amplifier (CGLNA) is described, with a noise figure (NF) based on Global Foundries and enhanced linearity and frequency response. It is reported that 0.13-µm CMOS technology. The design Combined with folded cascode with gain boosting LNA and common source stage of conventional split inductor stage. At a frequency of 4 GHz, the LNA circuit achieves a high gain of 22.11 dB with an input return loss of -24.86 dB and a flat NF of 0.3 dB. The linearity parameter IIP3 and 1 dB compression are improved -15.62 dBm and -22.69 dBm.

Systematic analysis of the principles and application scenarios of Low-Noise Amplifier

As society advances, new ideas and products are increasingly integrated into our daily lives. 5th generation mobile networks tech enables faster, lag-free connectivity, raising performance standards for components like Low-Noise Amplifiers. Summarizing Low-Noise Amplifier tech and applications helps researchers and firms leverage past knowledge and explore innovations. This paper analyzes Low-Noise Amplifier development and application, discussing types, principles, key performance indicators, and circuit structures of basic amplifiers. Five vital Low-Noise Amplifier characteristicsnoise figure, impedance matching, linearity, stability, and gainare examined. The author introduces design and application cases in radio astronomy, navigation systems, and 5th generation mobile networks communications based on Low-Noise Amplifier characteristics and performance requirements. The author concludes that advancing radio frequency tech requires improved Low-Noise Amplifiers, especially for high-frequency signals in 5th generation mobile networks. Promising noise performance enhancements come from technologies like modified high electron mobility transistors on GaAs and InP substrates. Monolithic Microwave Integrated Circuit integration reduces size while maintaining cost-effective performance. Future advancements in these areas could further boost Low-Noise Amplifier performance.

A Low-power, High-gain and Excellent Noise Figure GaN-on-SiC LNA Monolithic Microwave Integrated Circuit (MMIC) operating at Ka-band for 5G/6G Application

A 25-40 GHz monolithic low-noise amplifier (LNA) is designed and fabricated with the 100 nm gallium nitride on silicon carbide (GaN-on-SiC) technology. This four-stage-cascade monolithic LNA performs a low DC power consumption of 150 mW and noise figure of 1.6-2.2 dB. Moreover, the gain of 34-37 dB with the continuous wave of more than 2 W over 24 hours can be achieved covering the operating bandwidth. Hence, this state-of-art LNA possesses a great potential to be directly integrated with GaN power amplifiers and other microwave components to realize the high-integration, high-reliability, and high-power RF front-end.

A 22 nm CMOS 2.4 GHz 40.91 dB voltage gain RX front-end design

This briefing introduces a receiver (RX) front-end integrated with a virtual switch-based transmit/receive switch (TRSW) and a reconfigurable capacitor cross-coupled low noise amplifier (LNA) that employs the gain control scheme of direct shunt. Simulation and testing results indicate that the TRSW has an insertion loss of 0.2 dB and an isolation of 30 dB. The LNA achieves a maximum voltage gain of 40.91 dB or a power gain of 31.91 dB, a minimum S11 of −18.5 dB, and an input third-order intercept point of −22 dBm. The LNA consumes 2 mA from a 0.9 V power supply and has a minimum NF of 2.97 dB.

Influence of the Gain–Bandwidth of the Front-End Amplifier on the Performance of a QEPAS Sensor

The quartz tuning fork used as an acoustic sensor in quartz-enhanced photo-acoustic spectroscopy gas detection systems is usually read out by means of a transimpedance preamplifier based on a low-noise operational amplifier closed in a feedback loop. The gain–bandwidth product of the operational amplifier used in the circuit is a key parameter which must be properly chosen to guarantee that the circuit works as expected. Here, we demonstrate that if the value of this parameter is not sufficiently large, the response of the preamplifier exhibits a peak at a frequency which does not coincide with the series resonant frequency of the quartz tuning fork. If this peak frequency is selected for modulating the laser bias current and is also used as the reference frequency of the lock-in amplifier, a penalty results in terms of signal-to-noise ratio at the output of the QEPAS sensor. This worsens the performance of the gas sensing system in terms of ultimate detection limits. We show that this happens when the front-end preamplifier of the quartz tuning fork is based on some amplifier models that are typically used for such application, both when the integration time of the lock-in amplifier filter is long, to boost noise rejection, and when it is short, in order to comply with a relevant measurement rate.

A Cryogenic Wideband (2.5–14 GHz) Receiver System for the Arecibo Observatory 12 m Telescope

AbstractIn this paper we present details of the construction of a wideband, cryogenic receiver and its successful commissioning on the Arecibo Observatory 12 m telescope. The cryogenic receiver works in the 2.5–14 GHz frequency range. We upgraded the current narrow band, room temperature receivers of the telescope with the new wideband receiver. The current receiver is built around a Quadruple‐Ridged Flared Horn (QRFH) developed by Akgiray et al. (2013, https://doi.org/10.1109/tap.2012.2229953). To mitigate strong radio frequency interference (RFI) below 2.7 GHz, we installed a highpass filter before the first stage low noise amplifier (LNA). The QRFH, highpass filter, noise coupler and LNA are located inside a cryostat and are cooled to 15 K. The measured receiver temperature is 25 K (median value) over 2.5–14 GHz. The system temperature measured at zenith is about 40 K near 3.1 and 8.6 GHz and the zenith antenna gains are 0.025 and 0.018 K/Jy at the two frequencies respectively. We recommend the following improvements to the telescope system: (a) Upgrade the highpass filter to achieve better RFI rejection near 2.5 GHz; (b) Improve aperture efficiency at 8.6 GHz; (c) Upgrade the intermediate frequency system to increase the upper frequency of operation from 12 to 14 GHz.

WITHDRAWN: An 81MV/s SR, ±12.5V Swing Operational Amplifier with 2.15nV/√Hz Noise floor

—This brief introduces a high-voltage, high-speed and low-noise operational amplifier designed with a standard BCD process. High noise performance is achieved by using the bipolar transistors as input stage. However, the significant parasitic capacitance of the bipolar transistors leads to slew rate (SR) deterioration bandwidth deterioration. To overcome these problems, an improved folded-cascode structure with bipolar-based source degeneration current mirror (BSD-CM), the mirror pole control technique and the fast response output stage is proposed. The simulation results show that the BSD-CM improves the bandwidth by 35dB compared to the traditional bipolar current mirror. The mirror pole control improves the bandwidth of amplifier by 9dB. The fast response output stage improves the SR by 2 times. The proposed amplifier is fabricated with a standard 0.18 μm BCD process. The chip area is 3.75 mm2. The measurement results show that this amplifier consumes 4.5 mA with a ±15 V voltage supply. The SR is 81MV/s, the GBW is 158MHz and the input referred noise is 2.15 nV/√Hz.

Low-noise cryogenic microwave amplifier characterization with a calibrated noise source.

Parametric amplifiers have become a workhorse in superconducting quantum computing; however, research and development of these devices has been hampered by inconsistent and, sometimes, misleading noise performance characterization methodologies. The concepts behind noise characterization are deceptively simple, and there are many places where one can make mistakes, either in measurement or in interpretation and analysis. In this article, we cover the basics of noise performance characterization and the special problems it presents in parametric amplifiers with limited power handling capability. We illustrate the issues with three specific examples: a high-electron mobility transistor amplifier, a Josephson traveling-wave parametric amplifier, and a Josephson parametric amplifier. We emphasize the use of a 50-Ω shot noise tunnel junction (SNTJ) as a broadband noise source, demonstrating its utility for cryogenic amplifier amplifications. These practical examples highlight the role of loss as well as the additional parametric amplifier "idler" input mode.

Ultra-wideband low noise amplifier using resistive feedback and current reause

Ultra-wideband low noise amplifier using resistive feedback and current reause

N77 Radio Frequency Power Amplifier Module for 5G New-Radio High-Power User Equipment Mobile Handset Applications

This paper presents a highly efficient 5G New-Radio (NR) RF power amplifier module (PAM). The n77 PAM consists of a high-voltage differential-topology 2 μm GaAs HBT power amplifier, a CMOS controller, a silicon-on-insulator (SOI) switch, an integrated passive device (IPD) bandpass filter, a low-noise amplifier (LNA), and a bi-directional coupler. This PAM generates a saturation output power of 32.7 dBm including the loss of the SOI switch and output filter. The designed n77 PAM is tested with a commercial envelope tracker IC (ET-IC). The designed PAM with an ET-IC achieves an ACLR of −37 dBc at a 27 dBm output power with a DFT-s-OFDM QPSK 100 MHz NR signal and saves a dc power consumption of 950 mW compared to the APT mode. For the CP-OFDM 256QAM with the most stringent EVM requirements, it achieves an EVM of 1.22% at 23 dBm and saves 640 mW compared to the APT mode.

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

0.36 μW/channel capacitively-coupled chopper instrumentation amplifier in EEG recording wearable devices for compressed sensing framework

We evaluated the effectiveness of a low-current-consumption amplifier for a compressed-sensing (CS) framework in wearable electroencephalography (EEG) recording devices. The amplifier uses a capacitively coupled chopper instrumentation amplifier (CCIA) architecture which is often used for low-noise amplifier (LNA) to achieve low consumption and low-noise characteristics. According to measurements of the designed CCIA, the power consumption was 0.36 μW/channel, and the input referred noise (IRN) was 4.47 μVrms. The measured IRN and simulations were used to confirm the effect of CCIA noise on the CS-based EEG measurement framework. The difference in the normalized mean squared error at CR = 4 to the uncompressed conditions could be reduced to 0.008. The findings show that even with the LNA specialized for low power consumption, a slight signal degradation is observed when the compression ratio is increased up to 4 in the CS framework by utilizing the sparsity of EEG in the frequency domain.

A Low-Noise Amplifier for Submarine Electric Field Signal Based on Chopping Amplification Technology.

In the exploration of ocean resources, the submarine electric field signal plays a crucial role through marine electromagnetic methods. However, due to the field signal's low-frequency and weak characteristics, it often encounters interference from the instrument's own 1/f noise during its acquisition. To address this issue, we developed a low-noise amplifier for the submarine electric field signal based on chopping amplification technology. This amplifier utilizes low-temperature electronic components to adapt to the cold submarine environment and enhances its independence by incorporating a square wave generator. Additionally, we conducted simulations and experimental tests on the designed chopper amplifier circuit, evaluating the equivalent input voltage noise spectrum (EIVNS) and the frequency response within 1 mHz~100 Hz. The experimental results indicate that the amplifier designed in this study achieves sufficiently low noise 2 nV/√Hz@1 mHz, effectively amplifying the submarine electric field signal measured with the electric field sensor.

Power-to-Noise Optimization in the Design of Neural Recording Amplifier Based on Current Scaling, Source Degeneration Resistor, and Current Reuse.

This article presents the design of a low-power, low-noise neural signal amplifier for neural recording. The structure reduces the current consumption of the amplifier through current scaling technology and lowers the input-referred noise of the amplifier by combining a source degeneration resistor and current reuse technologies. The amplifier was fabricated using a 0.18 μm CMOS MS RF G process. The results show the front-end amplifier exhibits a measured mid-band gain of 40 dB/46 dB and a bandwidth ranging from 0.54 Hz to 6.1 kHz; the amplifier's input-referred noise was measured to be 3.1 μVrms, consuming a current of 3.8 μA at a supply voltage of 1.8 V, with a Noise Efficiency Factor (NEF) of 2.97. The single amplifier's active silicon area is 0.082 mm2.

A low-noise class AB amplifier fabricated by 180 nm BCD process for servo circuit of quartz flexible accelerometer

Quartz Flexible Accelerometer (QFA) system has gained extensive utilization in related navigation system due to the high precision, exceptional stability, and rapid response. The operational amplifier as the pivotal component of the analog servo circuit intricately relative to the performance of the QFA system. In this paper, the electrical mechanism of the QFA readout system and the influence of operational amplifier noise on the noise of QFA readout system is studied, a low-noise Class AB amplifier for the servo circuit of QFA readout system designed and fabricated by 180 nm BCD process, and the QFA readout system with the designed amplifier is simulated. The experimental results show that the low-noise amplifier achieved equivalent input current and voltage noise of 5.75pA/sqrt (Hz) and 12.7nV/sqrt (Hz) separately. Simulation results shows the designed QFA servo circuit has achieved resolution of 35 μ g and noise of 2.1 μ g/sqrt (Hz) @1Hz.

An analytical approach to designing millimeter‐wave LNAs with transformer‐based matching networks

AbstractIn this article, an analytical method for designing transformer matching network of millimeter‐wave (mm‐wave) low noise amplifier (LNA) is presented. In the circuit design, neutralizing capacitors (NCs) structure is used to mitigate the intrinsic gate‐drain feedback capacitance in the transistor for increasing the reverse isolation and available gain, thus allowing the common source (CS) structure can be regarded as an unilateralized active amplification part. The equivalent circuit of the active amplification part and the matching transformer network is modeled, then the analytical matching equations can be established, and the required matching transformer parameter can be determined quickly. As a proof of concept, a Ka‐band LNA operating at 37–43 GHz is designed and implemented in 65 nm complementary metal oxide semiconductor. The measured results show that the small signal gain of the circuit is 19.2–20.5 dB at 37–43 GHz. The noise figure (NF) in the operating band is 3.2–4.2 dB, and the minimum NF is 3.2 dB at 40.2 GHz. The chip area is only 0.08 mm2 excluding pads.

500-kHz Bandwidth Feedback for Scanning Ion Conductance Microscopy With Nanoresolution

Scanning ion conductance microscopy (SICM) has been developing rapidly and has been a versatile tool for nanoscale imaging. However, the imaging quality and scanning speed of SICM have been significant restriction factors for its various applications. One of the main reasons is the mutual restriction of bandwidth and noise of the ion current feedback. In this paper, a low-noise two-stage transimpedance amplifier (TIA) with 500 kHz bandwidth was proposed and a low-capacitance pipette was combined to depress the high-frequency ion current noise of SICM's feedback circuit. The effect of pipette capacitance, which is a major cuase of high-frequency noise, was significantly reduced by covering a thin polydimethylsiloxane (PDMS) film on the outer wall of the pipette. Finite element method (FEM) was employed for the first time to simulate the pipette capacitance model. Impedance spectroscopy experiments verified that this method can greatly reduce the pipette capacitance (about 0.7 times). Through the comparative analysis of ion current noise, as well as the scanning experiments of standard silicon material sample and PMDS sample, it was demonstrated that the proposed method has a significant effect in reducing the high frequency noise of ion current measurement. Therefore, our method can provide an avenue to realize high-speed imaging with high positioning accuracy.