Low Noise Amplifier Research Articles

Analysis and Design of Low-Noise Radio-Frequency Power Amplifier Supply Modulator for Frequency Division Duplex Cellular Systems

This paper describes an analysis of power supply rejection and noise improvement techniques for an envelope-tracking power amplifier. Although the envelope-tracking technique improves efficiency, its power supply rejection ratio is much lower than that of average power tracking or a fixed-supply power amplifier. In FDD systems with the envelope-tracking technique, the low power supply rejection ratio generates much output noise in the RX band and degrades the receiver’s sensitivity. An SM is designed by using a 130 nm CMOS process, and the chip die area is 2 × 2 mm2 with a 25-pin wafer-level chip-scale package. The designed SM achieved peak efficiencies of 78–83% for LTE signals with a 5.8 dB PAPR and various channel bandwidths. For the low-output-noise-supply modulator, noise reduction techniques using resonant-frequency tuning and a notch filter are employed, and the measured results show maximum 1.8/5/5.3/3.8/3 dB noise reduction in LTE bands B17/B5/B2/B3/B7, respectively.

DESIGN OF A 24.5 GHZ CMOS LOW NOISE AMPLIFIER USING 0.13-µM TECHNOLOGY FOR 6G WIRELESS APPLICATIONS

The need for high-performance circuit designs is growing as wireless communication technologies continue to advance and support newer generations of wireless applications. Much emphasis has been focused on the possibility of the 24 GHz frequency band in next-generation wireless networks, including 5G and beyond. Designing a low noise amplifier (LNA) operating at 24 GHz presents several challenges. The primary concerns include achieving high gain, low power consumption, low noise figure, and while maintaining good linearity and stability. This paper presents the design, simulation, and layout of a CMOS LNA optimized for operation at 24.5 GHz frequency, targeting 6G and beyond wireless communication applications. The proposed LNA employs three stages with a cascode topology at the first stage and follow by a common source stage at second and third stage. The three stages help to achieve high gain, and the source degeneration inductor at the first stage helps to improve linearity. Extensive simulations were conducted using a 0.13-µm CMOS technology, demonstrating a peak gain of 21 dB and a noise figure of 5.6 dB at 24.5 GHz. The LNA also exhibits good linearity and stability over a wide bandwidth. The performance metrics were validated through simulation and comparison, showcasing the feasibility of the designed LNA for 6G applications. This work contributes to the advancement of CMOS-based radio frequency (RF) front-end designs for next-generation wireless communication systems.

A compact 5-Watt low-loss and low-leakage reflective limiter for C-band

This paper introduces a reflective, low insertion loss transistor-based limiter based on a new leakage reduction method. The effectiveness of the proposed limiter has been confirmed through simulation and measurement results. Due to its low insertion loss, the proposed limiter is suitable for low-noise receivers. It reflects approximately 70% of the input power, leading to lower temperature rise, when subjected to high incident power, compared to absorptive limiters. Fabricated using a low-noise 0.15-μm AlGaAs–InGaAs pseudomorphic HEMT (pHEMT) technology, this design allows for co-design with a low noise amplifier (LNA) on the same die. Measurement results have demonstrated that the proposed limiter can withstand up to 5-W continuous-wave (CW) input power without failure in a compact chip area of only 0.8 mm2. Additionally, measurements show a minimum insertion loss of 0.83 dB with 0.17 dB ripple over the frequency range of 4–6 GHz.

Enhancing Low Energy Technology Performance: Optimizing Low Noise Amplifier through Stabilization and Input-Output Component Matching Design

Enhancing Low Energy Technology Performance: Optimizing Low Noise Amplifier through Stabilization and Input-Output Component Matching Design

Investigation of Superconducting Quantum Interference Readout Electronics Based on Self-Feedback Differential Low-Noise Amplifier

Investigation of Superconducting Quantum Interference Readout Electronics Based on Self-Feedback Differential Low-Noise Amplifier

A 26‐GHz Low Noise Amplifier With 1.6‐dB Minimum Noise Figure in 0.15‐μm GaN‐on‐SiC Process

ABSTRACTA 24.8–29.1‐GHz four‐stage gallium nitride (GaN) low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) is presented in this letter which is fabricated in a 0.15‐μm GaN‐on‐SiC process. The proposed GaN LNA utilizes gate/drain bypass networks and source degeneration (SD) to achieve both 0–40‐GHz unconditional stability and broadband simultaneous noise and input matching (SNIM). The measured results show a peak gain of 19.9 dB with a 3‐dB bandwidth of 4.3 GHz and a low noise figure (NF) of 1.58–2.57 dB. The input and output return losses are better than 11 dB and the output‐referred third‐order intercept point (OIP3) is greater than 21 dBm. The presented LNA has a core area of 4.2 mm2 and consumes a power dissipation of 150 mW. Compared with other state‐of‐the‐art GaN LNA designs, the proposed LNA exhibits competitive NF and overall performance.

A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based Electrostatic Discharge Protection for 60 GHz Applications

This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection.

Optimization Analysis of Low-Noise Amplifier

This paper mainly analyzes the important component of a wireless receiver – low-noise amplifiers (LNA). Low-noise amplifiers can reduce the effect of noise on the received signal and amplify signals. For the better development of wireless communication technology, remote control, and other related fields, it is necessary to optimize the design of low-noise amplifiers, so that low-noise operational amplifiers can finally obtain high gain, low noise figure, and other advantages. This paper analyzes the optimization design of LNA in the field of Global Navigation Satellite Systems (GNSS). This paper analyzes a low-noise amplifier design with the operation of concurrent dual-band for GNSS receivers with a single channel. The optimized design of a low-noise amplifier in this field uses a low-cost 0.18µm CMOS tube and adds load capacitances and a feedforward path to reduce the noise figure (NF) of the system. Noise figures in 1.2 GHz and 1.57 GHz bands are reduced by about 0.9 dB. In addition, the high gain, high linearity, and other excellent properties are shown in 1.2 GHz and 1.57GHz. In the application of 5G/6G network technology, the optimized design of Gallium Arsenide (GaAs) PHEMT technology with a gate length of 0.3µmm and inductively degraded common source topology phase structure is adopted. From this optimization, the noise figure is optimized to 1.3-1.4, and the gain of the system is 20-22 dB. At the same time, good linearity is also shown. Then, the prospects of semiconductor materials such as Gallium Nitride (GaN) and Indium Phosphide (InP), which have the advantages of high electron mobility and low-cost design, in optimizing low noise operational amplifiers. To a certain extent, the in-depth study of the optimal design of LNA can improve the technical level of wireless communication, aerospace, and other fields.

A 23–29 GHz GaN Low-Noise Amplifier with Drain-to-Source Coupling Feedback

In this paper, a four-stage gallium nitride (GaN) low noise amplifier (LNA) using coupled-line (CL) feedback in a 0.15-μm GaN-on-SiC process is proposed. The electromagnetic coupling feedback between the drain and source of each transistor is employed to generate an additional signal path for neutralization, which enhances gain and improves stability performance. A series transmission line-capacitor-transmission line (TL-C-TL) network is introduced between stages of the LNA for wider band interstage matching. The measured results show that the designed LNA achieves a 3-dB bandwidth of 23.6 to 29.8 GHz, a peak gain of 23.7 dB at 25.8 GHz, and a minimum noise figure (NF) of 2.2 dB at 27.8 GHz. The output-referred 1-dB compression point (OP1dB) is 13 dBm. The total power consumption of the LNA is 200 mW.

Dual-Band Low-Noise Amplifier for GNSS Applications

A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively.

Magneto-acousto-electrical tomography based on frequency response compensated linearly frequency-modulated signal stimulation

Objective. In magneto-acousto-electrical tomography (MAET), linearly frequency-modulated (LFM) signal stimulation uses much lower peak voltage than the spike pulse stimulation, lengthening the operation life of the transducer. However, due to the uneven frequency responses of the transducer, the low-noise amplifier (LNA), and the bandpass filter (BPF), MAET using LFM signal stimulation suffers from longitudinal resolution loss. In this paper, frequency response compensated linearly frequency-modulated (FRC-LFM) signal stimulation is investigated to resolve the problem.Approach. The physical model of measurement of the frequency responses of the transducer and the cascading module of the detection electrodes, the LNA, and the BPF is constructed. The frequency responses are approximated by fitting a curve to the measurement data. The frequency response compensation function is set to the reciprocal of the product of the frequency responses. The digital FRC-LFM signal is generated in MATLAB and converted to analog signal through an arbitrary waveform generator. Two groups of MAET experiments are designed to confirm the performance of the FRC-LFM signal stimulation. Pure agar phantom with rectangular through-holes and agar phantom with pork tissue inclusion serve as the samples.Main results. The pulse-compressed magneto-acousto-electrical signal obtained using FRC-LFM stimulation has narrower main-lobe than that obtained using LFM excitation, although the signal to noise pulse interference ratio of the former is little lower than that of the latter, which is due to the limitation of the power amplifier. FRC-LFM also proves to be an effective method to utilize the frequency outside the working band of the transducer in MAET.Significance. The method in this study compensates for the longitudinal resolution loss due to the uneven frequency responses. Combining with high-capability power amplifier and high-performance LNA, the MAET using FRC-LFM signal stimulation can potentially achieve high longitudinal resolution and high sensitivity, advancing MAET toward the clinical application.

Single-Input Multiple-Output (SIMO) Cascode Low-Noise Amplifier with Switchable Degeneration Inductor for Carrier Aggregation.

This paper presents a single-input multiple-output (SIMO) cascode low-noise amplifier with inductive degeneration for inter- and intra-band carrier aggregation. The proposed low-noise amplifier has two output ports for flexible operation in carrier aggregation combinations for band 30 and band 7. However, during inter- and intra-band operation, gain variation occurs depending on the output mode. To compensate for this, a switching circuit is proposed to adjust the degeneration inductor, optimizing gain performance for both modes. The switching operation can minimize the control for the dynamic range in the receiver system to support carrier aggregation. The designed low-noise amplifier was fabricated using a 65 nm CMOS process, occupying an area of 2.1 mm2. In inter-band operation, the small-signal gain was measured by 18.9 dB for band 30 and 18.6 dB for band 7, with the noise figures of 1.03 dB and 1.07 dB, respectively. For intra-band operation, the small-signal gain was 17.3 dB and 17.2 dB, with the noise figures of 1.3 dB and 1.41 dB. The IIP3 values were measured by -7.6 dBm and -6.7 dBm for inter-band, and -6.3 dBm and -6.2 dBm for intra-band. Power consumption was 8.04 mW and 7.68 mW in inter-band, and 17.04 mW and 17.64 mW in intra-band depending on the output configuration.

Aspect ratio optimization of piezoelectric extensional mode resonators for quality factor and phase noise performance enhancement

Abstract This study focuses on optimizing the resonator geometry via the aspect ratio design of a width-extensional mode resonator to improve its quality factor (Q), which is one of the critical performance parameters for resonators in either sensing (Allan deviation) or frequency reference (phase noise) applications. The proposed approach uses finite element analysis to reduce the strain energy at anchor supports by altering the resonator geometric structure, thereby reducing energy loss through anchors. Moreover, process limitations on feature sizes are used as constraints to find aspect ratios that can not only increase the Q but also reduce spurious modes near the targeted frequency. The devices were fabricated using AlN thin film piezoelectric on a substrate (TPoS) process. The simulated energy dissipation trends for specific length-to-width (L/W) ratios closely match the measured changes in the resonator Q values in vacuum. In vacuum, the highest Q-factor achieved by the device is close to 8816, with a motional resistance of a few tens of ohms. Additionally, a board-level oscillator realized using a commercial low-noise amplifier exhibits phase noise performance of −141.21 dBc Hz−1 and −164.25 dBc Hz−1 at 1 kHz and 1 MHz frequency offsets, respectively. The calculated figures of merit for these offsets are 204 and 168, respectively.

A Compact V-Band Temperature Compensation Low-Noise Amplifier in a 130 nm SiGe BiCMOS Process.

This paper presents a compact V-band low-noise amplifier (LNA) featuring temperature compensation, implemented in a 130 nm SiGe BiCMOS process. A negative temperature coefficient bias circuit generates an adaptive current for temperature compensation, enhancing the LNA's temperature robustness. A T-type inductive network is employed to establish two dominant poles at different frequencies, significantly broadening the amplifier's bandwidth. Over the wide temperature range of -55 °C to 85 °C, the LNA prototype exhibits a gain variation of less than 1.5 dB at test frequencies from 40 GHz to 65 GHz, corresponding to a temperature coefficient of 0.01 dB/°C. At -55 °C, 25 °C, and 85 °C, the measured peak gains are 25.5 dB, 25 dB, and 24.4 dB, respectively, with minimum noise figures (NF) of 3.0 dB, 3.5 dB, and 4.2 dB, and DC power consumptions of 22.3 mW, 27.6 mW, and 34.4 mW. Moreover, the total silicon area of the LNA chip is 0.37 mm2, including all test pads, while the core area is only 0.09 mm2.

Magnetic resonance microscopy for submillimeter samples in a horizontal MR scanner

The spatial resolution in magnetic resonance imaging is mainly limited by low SNR, which is commonly addressed by long measurement times or dedicated hardware. In single digit micron resolutions, diffusion becomes a further limiting factor since depending on the gradient strength, the diffusion length of particles may approach the target resolutions. Spatial resolution improvement has been addressed by microscopy inserts comprising dedicated gradient systems and RF-coils, usually designed for NMR spectrometers that are often equipped with a deuterium lock for field drift compensations. The presented microscopy insert has been designed to provide single-digit micron resolutions on horizontal preclinical imaging systems utilizing their full imaging and user interface capabilities. The incorporated gradient provides an efficiency of 0.135 T/(m∙A) which in combination with the system’s gradient amplifiers yields a maximum of 27 T/m. With the additional low noise amplifier added to the RF-path a three-fold SNR improvement could be achieved for small samples. Furthermore, a modified constant time imaging sequence was introduced to improve the capability of the setup for ultra‐high-resolution imaging demonstrated on zebrafish embryos at different development stages with (9 μm)³ resolution.

Radiation influence on planar reconfigurable field effect transistor low noise amplifier performance

Abstract Many novel devices have been proposed in the literature to mitigate the short channel effect and the reconfigurable FET (RFET) is one of them. The circuits based on new devices need to be investigated when they are introduced. This work has two parts: (i) designing cascoded RFET low noise amplifiers (LNA) and their performance analysis; and (ii) single-event performance analysis of RFET-LNAs. The designed LNA has a gain of 12 dB and a noise figure of 2.42 dB. The device in the common gate configuration mode is more susceptible to heavy ion radiation and collects more charge (QC) compared to the device in the common source configuration mode. Through temporal and frequency analysis, the irradiation disturbance is examined. In the temporal analysis, the collected charge (QC) is used as a metric, and the spectrogram is used in the frequency analysis.

Performance Evaluation of Matching Networks in Low Noise Amplifiers for GPS Application

Performance Evaluation of Matching Networks in Low Noise Amplifiers for GPS Application

A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems

With the advance in wireless communication, next-generation software-defined radio (SDR) systems require transceivers to operate in both sub-6GHz and millimeter-wave (mmWave) band and support multiple standards. However, bridging sub-6GHz frequencies with millimeter-wave bands exceeding 30 GHz remains a challenge for conventional wideband LNAs. To surmount this, a 2–36 GHz CMOS low-noise amplifier (LNA) designed for SDR systems is introduced in this paper. An innovative wideband input matching network capable of spanning both frequency domains is proposed. The methodology effectively mitigates the impact of vast parasitic capacitances, achieving wideband input matching against Electrostatic Discharge (ESD) and on-chip decoupling capacitor parasitic. In addition, a π-network-based wideband interstage matching technique is adopted to extend bandwidth of gain. A tri-stage prototype of the proposed LNA, designed using a 40-nm CMOS process, is designed to validate our design strategies. The post-simulation outcomes reveal a peak gain of 14 dB with a -3dB bandwidth ranging from 2 to 36 GHz, equating to a fractional bandwidth of 178 %. The Noise Figure (NF) is commendably uniform across the frequency spectrum, stabilizing at 5 dB. Furthermore, the third-order input intercept point (IIP3) is −4.2dBm to -3dBm across the bandwidth. The performance is achieved with a power of 19.4 mW and within a core area of 0.1 mm2.

Analyzing the Indirect Effects of Lightning on Unmanned Aerial Vehicle Navigation Receivers

To investigate the interference effects of lightning on unmanned aerial vehicle (UAV) navigation receivers, an analytical approach for the evaluation of indirect lightning effects is suggested. The blocking mechanism of lightning pulses on the receiver is analyzed using the vector method. A behavioral-level simulation model of the receiver’s radio frequency (RF) front-end is constructed, and a lightning pulse injection simulation is performed based on the advanced design system (ADS). The simulation results indicate that lightning pulses induce blocking interference on the RF front-end of the navigation receiver, reducing its sensitivity and dynamic range. This interference is attributed to gain compression and degradation of the noise figure in the low-noise amplifier (LNA). To further validate the simulation results, a pin injection test is carried out to examine the influence of lightning pulses with different peak voltages on receiver sensitivity. The test results indicate a notable reduction in the receiver sensitivity when the lightning pulse peak reaches 250 V. The sensitivity trends across various test panels are consistent, and the damage thresholds are similar. These findings confirm the accuracy of the simulation results.

A 28 GHz balun‐first LNA with db‐linear 32 db gain range for 5 G applications

AbstractThis letter presents a 28 GHz balun‐first low noise amplifier (LNA) featuring a wide dB‐linear variable gain range. The architecture of LNA includes three‐stage cascode amplifiers. An integrated balun at the input stage provides RF ESD protection and converts a single‐ended signal to a differential one (S‐to‐D). A transformer‐based dual‐resonant matching network is designed and analyzed to achieve wideband performance. To realize a continuous dB‐linear variable gain range and consistent input/output matching, gain control is implemented in the second stage using a 5‐bit digital‐to‐analog converter (DAC) for a 32 dB gain range. The DAC can generate a nonlinear analog voltage to control the gate of the common‐gate transistor in the second cascode stage, inversely compensating for the nonlinear gain variations of the cascode amplifier. The LNA is fabricated in 65‐nm CMOS process with a core size of 0.154 mm². Measurement results exhibit a maximum gain of 33.5 dB and a minimum noise figure (NF) of 3.65 dB with a 3‐dB bandwidth of 23–29.5 GHz. The measured variable gain range is approximately 32 dB across 32 different gain states, with a linear gain step of ~1 dB per state and an IP1dB ranging from −6.5 dBm to −35.25 dBm. The power consumption is 35.4–48 mW from a 1.2 V supply voltage.