A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based Electrostatic Discharge Protection for 60 GHz Applications

Abstract

This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection.