A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems

Abstract

With the advance in wireless communication, next-generation software-defined radio (SDR) systems require transceivers to operate in both sub-6GHz and millimeter-wave (mmWave) band and support multiple standards. However, bridging sub-6GHz frequencies with millimeter-wave bands exceeding 30 GHz remains a challenge for conventional wideband LNAs. To surmount this, a 2–36 GHz CMOS low-noise amplifier (LNA) designed for SDR systems is introduced in this paper. An innovative wideband input matching network capable of spanning both frequency domains is proposed. The methodology effectively mitigates the impact of vast parasitic capacitances, achieving wideband input matching against Electrostatic Discharge (ESD) and on-chip decoupling capacitor parasitic. In addition, a π-network-based wideband interstage matching technique is adopted to extend bandwidth of gain. A tri-stage prototype of the proposed LNA, designed using a 40-nm CMOS process, is designed to validate our design strategies. The post-simulation outcomes reveal a peak gain of 14 dB with a -3dB bandwidth ranging from 2 to 36 GHz, equating to a fractional bandwidth of 178 %. The Noise Figure (NF) is commendably uniform across the frequency spectrum, stabilizing at 5 dB. Furthermore, the third-order input intercept point (IIP3) is −4.2dBm to -3dBm across the bandwidth. The performance is achieved with a power of 19.4 mW and within a core area of 0.1 mm2.