Low Noise Amplifier Research Articles

Low noise amplifier design for hidden wireless lan applications using band pass filter with geometric mean prototype element values

Low noise amplifier design for hidden wireless lan applications using band pass filter with geometric mean prototype element values

A 5.6-dB Noise Figure, 63–86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation

A 5.6-dB Noise Figure, 63–86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation

Optimizing Low Noise Amplifiers: A Two-Stage Approach for Improved Noise Figure and Stability

Optimizing Low Noise Amplifiers: A Two-Stage Approach for Improved Noise Figure and Stability

High Precision Ping-Pong Auto-Zeroed Lock-in Fluorescence Photometry Sensor.

This paper presents a high-precision CMOS fluorescence photometry sensor using a novel lock-in amplification scheme based on switched-biasing and ping-pong auto-zeroing techniques. The CMOS sensor includes two photodiodes and a lock-in amplifier (LIA) operating at 1 kHz. The LIA comprises a differential low-noise amplifier using a novel switched-biasing ping-pong auto-zeroed scheme, an automatic phase aligner, a programmable gain amplifier, a band-pass filter, a mixer, and an output low-pass filter. The design is fabricated in 0.18-µm CMOS process, and the measurement shows that the LIA can retrieve noisy input signals with a dynamic reserve of 42 dB, while consuming only 0.7 mW from a 1.8 V supply voltage. The measured results show that the LIA can detect a wide range of incident light power from 8 nW to 24 µW. The proposed design is encapsulated in a 3D-printed housing allowing for real-time invitro biomarker detection. This ambulatory platform uses an LED and a fiber optic to convey the excitation light to the sample and retrieve the fluorescence signal. Experiments with a beads solution diluted in PBS demonstrate that the sensor has a sensitivity of 1:100 k. Experimental results obtained invitro with NIH3T3 mouse cells tagged with membrane dye show the ability of the prototype to detect different densities of cell culture. The portable prototype, which includes optical filters and a small 30 mm × 36 mm × 30 mm printed circuit board enclosed inside the 3D-printed housing, consumes 36.7 mW and weighs 120 g.

Multi-parallel Differential JFET Low-Noise Amplifier Circuit Based on Discrete Current Source

Multi-parallel Differential JFET Low-Noise Amplifier Circuit Based on Discrete Current Source

A 4–22 GHz Ultra-Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and 28–31 dB Gain Enhanced by the Negative Load Impedance

A 4–22 GHz Ultra-Wideband Low-Noise Amplifier With 0.8–1.5 dB NF and 28–31 dB Gain Enhanced by the Negative Load Impedance

Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio

Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio

78.8 pJ/b, 100 Mb/s Noncoherent IR-UWB Receiver for Multichannel Neurorecording Implants.

In this article, we present a novel approach for designing a low-power, low-area impulse radio ultra-wideband (IR-UWB) noncoherent receiver capable of achieving a data rate of 100 Mbps. Our proposed receiver demonstrates the ability to demodulate ON-OFF keying pulse streams across the entire lower frequency band defined by the Federal Communication Commission for UWB applications. The key components of the proposed receiver include a reconfigurable differential two-stage low-noise amplifier, a fully differential squarer, narrow-band interface rejection filters, and variable gain baseband amplifiers. These circuits work cohesively to ensure efficient signal reception and processing. To validate the performance of the proposed receiver, we implemented the design using TSMC 40-nm CMOS process technology. A short-range communication including a 1.5 cm tissue layer is tested utilizing a typical upconversion UWB transmitter fabricated in the same technology. Remarkably, the proposed receiver achieves a data rate of 100 Mbps with an impressively low energy efficiency of 78.8 pJ/b and occupies an area of 0.705 mm2. The compact size, remarkable energy efficiency, and high data rate capabilities of the proposed receiver meet the stringent requirements of neural recording implants.

Sziklai Pair based Small signal Amplifier with bjt-mosfet Hybrid Unit at 180nm Technology

Two circuit models of Small Signal amplifier, constituted with BJT-MOSFET hybrid unit under Sziklai pair topology are designed and analyzed using ‘PSpice’ and ‘Cadence Virtuoso and Spectre simulation tool (at GPDK 180nm technology)’ respectively. First amplifier (Circuit-1) uses PSpice user-defined model of BJT and MOSFET whereas the second amplifier (Circuit-2) consists of transistors available at GPDK 180nm technology. Circuit-1 can amplify the AC signals of 1mV-1nV range with optimum voltage gain 389.532, 137.570 current gain, 14.464MHz bandwidth and 2.43% THD. However, Circuit-2 can amplify AC signals of 0.1mV-10nV range with 164.018 voltage gain, 32.775 current gain, 11.906 MHz bandwidth, and 13.608E-6% THD. Both the proposed amplifier circuits remove narrow band problem and generate better results than earlier announced small signal Sziklai pair amplifier with BJT-MOSFET hybrid unit in respect of voltage and current gains, bandwidth, THD, and power consumption. Proposed amplifiers successfully address the problem of poor frequency response of small signal Darlington pair amplifier in higher frequency range and narrow bandwidth limitations of small-signal PNP Sziklai pair amplifier. Dependency of the proposed amplifiers at various biasing resistances and performance with temperature variation, noise variation, DC supply variation, and phase variation are also discussed herein. Proposed Circuits display strong dependency over ideal maximum forward beta ‘β’ of NPN transistor, Transconductance ‘VTO’ of P-MOS transistor and additional biasing resistances ‘RA’. Layout of Circuit-2 is found to cover 96.3898µm2 area with 11.32µm length and 8.515µm breadth. Minor percentage variation between pre-layout and post-layout simulation results of Circuit-2 validates the proposed design at GPDK 180nm technology. Monte Carlo and Process Corner analysis are also performed to test the robustness and insensitivity of Circuit-2 against mean value of the parameters and process and mismatch respectively. Performance summary of the proposed circuits and comparison with the recently reported designs shows effectiveness of the proposed circuits in terms of power gain, THD, voltage gain, current gain, input referred noise and power gain. Qualitative analysis of the proposed Circuits recommends its usability as Low Noise Amplifier in the portable RF noise measurement system.

On-Chip Tunable Active Inductor Circuit for Radio Frequency Ics

The work presents a design of a gyrator-based on-chip tunable active inductor (AI) which can become an integral part of high-frequency integrated circuits. The proposed AI uses the Floating gate technology-based PMOS (FGPMOS) simulation model, where the on-chip, non-volatile programming ability of FGPMOS is used as a tunable active feedback resistor. The circuit specifications are first derived for the application at 800MHz to 2GHz. The design is simulated at 350nm CMOS technology and shows a temperature sensitivity of 0.13mV/oC as well as a noise sensitivity of about 10.97nV/Hz. The precise programming range of inductance value from 3nH to 9nH can be achieved. The circuit has a power dissipation of 5.02mV and a moderately high-quality factor of about 120. The layout of the proposed circuit has been designed on Cadence Virtuoso and fabricated at ON-Semiconductor, C5 CMOS process foundry of MOSIS fabrication service, USA. The complete design has a chip area of 18x30µm2. The fabricated results illustrate the on-chip tuning ability of the proposed AI from 3nH to 7nH with the help of externally applied Tunnelling and Injection voltages, respectively. The proposed design also simulates a tunable bandpass filter and a tunable Low Noise Amplifier.

A wideband low power RF Receiver Front-End for Internet-of-Things applications

This paper presents a broadband RF receiver front-end circuit that offers advantages in both area and power consumption. The design features an innovative dual-path noise-canceling Low-Noise Amplifier (LNA) circuit, achieving impedance matching and balun functionality without the need for on-chip inductors. The RF receiver front-end circuit comprises a I and Q doublebalanced quadrature passive mixers and an 25% duty-cycle LO generator. The circuit’s broadband characteristics enable it to operate across a wide range of frequency bands. It is implemented using a 65 nm CMOS process. The core circuit, including both RF and baseband signal paths, consumes a mere 12 mW of power. Test results demonstrate that the RF receiver front-end circuit achieves a conversion gain of 35–40 dB, a noise figure (NF) below 4.8 dB, and a minimum third-order intercept point (IIP3) exceeding −6.8 dBm over the 0.1–3.1 GHz frequency range. The chip’s overall footprint is compact at 0.9 mm2, with the entire RF signal path powered by a 1 V supply, offering clear advantages in terms of compactness and low power consumption.

An Ultra-wideband Low-power Low-noise Amplifier Linearized by Adjusted Derivative Superposition and Feedback Techniques

Ultra-wideband (UWB) applications require low-power and low-noise amplifiers (LNAs) that can operate over a wide frequency range. However, conventional LNAs often suffer from poor linearity and high-power consumption. This research work proposes a novel LNA design that uses the adjusted derivative superposition (DS) technique and feedback to improve the linearity and reduce the power consumption of UWB LNAs. The DS technique enhances the third-order intermodulation (IM3) cancellation by adjusting the bias currents of the transistors, whereas the feedback improves the stability and input matching of the LNA. The LNA is implemented using a degenerated common source topology in a 180 nm standard CMOS technology. The simulation results show that the LNA achieves a power gain of 10–12.2 dB, an input third-order intercept point (IIP3) of about 12 dBm, and a noise figure of less than 2.5 dB over the UWB frequency band of 3.1–10.6 GHz. The input reflection coefficient is less than -10 dB, and the power consumption is 11.6 mW with a 1.5 V power supply. The designed LNA offers a novel and innovative solution for UWB applications that significantly improve the performance and efficiency of UWB LNAs whereas reducing the cost and complexity of implementation.

A Comprehensive Study on Phase Sensitive Amplification and Stimulated Brillouin Scattering in Nonlinear Fibers with Longitudinally Varying Dispersion

Fiber optic parametric and phase sensitive amplifiers (PSA) are interesting for modern day communication technologies due to their low noise and high gain amplification properties with a potential for all optical signal processing and wide band operation. PSAs are typically employed in either a single pump or dual pump configuration. In this article we explore the utilities of both configurations, however considering a fiber with a longitudinally varying dispersion profile. For the single pump case, PSA operation at large pump-signal detunings, that arise due to the longitudinal dispersion variation, were studied numerically, and recipes of using the system as a wide band wavelength selective filter were laid out. For the dual-pump case, emphasis was laid on achieving a larger signal gain, by reducing stimulated Brillouin scattering (SBS) that prevents large pump power transport through the nonlinear fiber. First, the effects of dispersion variation on the gain of a dual pump PSA were studied analytically and numerically in order to optimize the dispersion variation profile, neglecting SBS processes. Then we independently studied the SBS dynamics of the system numerically. A sinusoidally dispersion oscillating fiber (DOF) was found to be an optimal candidate with respect to its PSA and SBS performances. To establish this claim, we also experimentally compared the performance of an available DOF over a standard highly nonlinear fiber (HNLF) that has a constant dispersion profile and established its utility for designing a high gain PSA system, thanks to the SBS mitigation due to the longitudinal dispersion variation of the fiber.

Design of a high bandwidth ECG signal low noise amplifier circuit for wearable devices

Nowadays, more than one million people die due to heart problems annually. Detecting the Electrocardiogram curve is an effective way to evaluate heart condition. Compared with large devices in the hospital, wearable devices are showing their advantage in detecting peoples Electrocardiogram whenever and wherever possible. However, in traditional amplifier circuit design, there is less attention to the bandwidth. The noise is negatively correlated with the current while the power consumption is positively correlated with the current, so it is challenging to balance the noise and power. Therefore, a design of a high bandwidth Electrocardiogram signal low noise amplifier circuit for wearable devices is proposed in this paper. The improved circuit is based on a conventional instrumentation amplifier and consists of two stages. The op-amps were replaced with Operational Transconductance Amplifier. The circuit also has a Driven-Right-Leg circuit part, which can tremendously reduce the effect of common-mode noise. The simulation result shows that the circuit has a high bandwidth and stable gain. Meanwhile, the circuit consumes less power and has a low integrated input-referred noise. This study is extremely helpful in expanding the application of wearable Electrocardiogram signal-detecting devices.

Research on Noise Optimization of CMOS Amplifier Used in ECG Signal

Electrocardiography has a wide range of applications in monitoring heart health and diagnosing diseases, among which how to efficiently and accurately reduce noise of electrocardiogram (ECG) signals is of great significance. This paper first writes the processing flow of ECG signals and the theoretical basis of low-noise CMOS amplifiers, then analyzes the difficulties of noise optimization of CMOS amplifiers in ECG scenarios, and then proposes feasible solutions for each difficulty. Considering these influencing factors comprehensively and using a variety of noise reduction methods in a reasonable combination will actively help the noise optimization of the ECG signal. Linking the CMOS amplifier with the noise reduction processing of the entire ECG circuit can reduce the interference of noise and improve the quality of the signal, so that the ECG signal can more accurately reflect the electrical activity of the heart. This is of great significance for the monitoring and research of heart health.

Analysis of Indirect Lightning Effects on Low-Noise Amplifier and Protection Design

In order to analyze the interference mechanisms of indirect lightning effects on a low-noise amplifier (LNA), a circuit model of the LNA was constructed based on the advanced design system 2020 (ADS 2020) software. Lightning pulse injection simulations were conducted to explore the influence of lightning pulses on the performance of the LNA. A pin injection test was performed to investigate the interference and damage threshold of the LNA. A protective circuit incorporating the transient voltage suppressor (TVS) and Darlington structure was designed through simulation, employing the ADS 2020 for the LNA. The research findings reveal that the interference threshold for the LNA is 60 V, while the damage threshold is determined to be 100 V. The protective circuit demonstrates a measured insertion loss of 0.1 dB, a response time of 1.5 ns, and a peak output voltage of 20 V. The research results indicate that the protective circuit can effectively reduce the impact of lightning’s indirect effects on the LNA. In the future, we will continue the design work of the protective circuit and proceed with physical fabrication and experimental validation.

A 28 nm CMOS low-noise amplifier with novel redundant noise cancellation technique beyond ultra-wideband for 6G-based wireless systems

In the current scenario, almost 5G-based wireless systems have been deployed everywhere but still performance trade-offs of RF amplifiers in the sub-nanometer regime are challenging. In this work, a high-performance low-noise amplifier (LNA) is realized in a 28 nm CMOS process with a novel redundant noise cancellation technique (RnC). The proposed technique improves the noise figure (NF) beyond the ultra-wideband of a low-noise amplifier (LNA) and minimizes the trade-off in the 28 nm process. An ultra-low NF is achieved in two approaches; Firstly, a current mirror network is employed in the primary path to cancel the thermal noise of the dominant transistor of a common gate-common source (CG-CS) without an extra power supply. Secondly, an auxiliary amplifier stage is introduced here to reduce the noise which contributes to the current mirror circuit and cancels the distortion in CG-CS topology without violating the traditional noise cancellation condition. In addition, an analytical approach is followed to optimize the input impedance, gain bandwidth and noise figure. Hence, the proposed RnC LNA benefits in achieving good tradeoffs among gain, bandwidth, NF, and power consumption in 28 nm technology node. The proposed RnC LNA is analyzed and fabricated using CMOS 28 nm technology, occupying an area of 0.011 mm2. The proposed design achieves an optimum performance: nearly flat gain of 15.3 dB, minimum NF of 1.7 dB over 1.7 to 12.52 GHz, and an IIP3 of − 2.6 dBm at 6.5 GHz. The proposed LNA consumes ultra-low power consumption of 1.8 mW under the power supply of 1 V.

Research on Low Noise Chopping Amplifier Circuit Based on Feedback Regulation

In order to overcome the limitation of 1/f noise on long-period magnetotelluric sensors, it is necessary to use low-noise chopping technology for signal conditioning. However, the static operating point drift of Junction Field-Effect Transistor (JFET) is difficult to achieve stable amplification with the chopper technology. This paper proposes a low noise amplifier (LNA) with chopper technology based on feedback adjustment. The LNA reduces the turning frequency of the circuit, and maintains the JFET static point. At 375mHz, its noise is 2.55nV/Hz .

Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks

A deep neural network architecture for the automatic sizing of analog circuit components is proposed, with a focus on radio frequency (RF) applications in the 2 to 5 GHz region. It addresses the challenges of the typically small number of examples for network training and the existence of multiple solutions, of which impractical values for integrated circuit implementation. We address these issues by restricting the learning to one component size at a time, thanks to a cascade of dedicated shallow neural networks (SNN), where each network constrains the prediction of the next ones. Moreover, the SNNs are individually tuned by a genetic algorithm for the prediction order and accuracy. This reduction of the solution space at each step allows the use of small training sets, and the introduced constraints between SNNs handle component interdependencies. The method is successfully validated on three different types of RF microcircuits: a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), and a mixer, using 180 nm and 130 nm CMOS implementations. All the predictions were within 5 % of the true values, both at the component and performance levels, and all the responses were obtained in less than 5 s, after 4 to 47 min. training on a regular PC station. The obtained results show that the proposed method is fast and applicable to arbitrary analog circuit topologies, with no need to retrain the developed neural network for each new set of desired circuit performances.

Development of a Prototype CMOS 0.18 μm Low-Noise Amplifier Chip for the Receiving Path of the NB-IoT system

Development of a Prototype CMOS 0.18 μm Low-Noise Amplifier Chip for the Receiving Path of the NB-IoT system