Low Gate Voltage Research Articles

Dielectric Modulated TFET on SELBOX Substrate as a Label-Free Biosensor Applications: Analytical Modeling Study and Sensitivity Analysis

Abstract The manuscript proposes a ferroelectric heterojunction TFET (BG-FE-HJ-STFET) on SELBOX substrates with a back gate to create an ultra-sensitive label-free biosensor with dielectric modulation for the detection of neutral and charged biomolecules. Within the proposed device, four cavities have been carved out for the biomolecules' immobilization under the front and rear gate dielectrics. By using a ferroelectric (FE) material as a gate stack, the low gate voltage is increased to be more effective by causing a negative capacitance phenomenon. The response of the proposed biosensor to four impartial biomolecules with different dielectric constants Protein (k=8), Biotin (k=2.63), 3-Aminopropyl-triethoxysilane (APTES) (k=3.57), and Streptavidin (k=0.1) has been investigated. Deoxyribonucleic acid (DNA), a charged biomolecule, is also examined for dielectric constant of k=6 with respect to both charges (Negative and Positive)) densities. The device is simulated with the commercially available SILVACO ATLASTM TCAD tool. The performance analysis relies on several figures of merit (FOMs) such as DC/RF and sensitivity (including drain current, ION/IOFF ratio, and subthreshold swing) for both neutral and charged biomolecules. The optimized cavity structure demonstrates a notable sensitivity in drain current (2.7x108) and a significant ION/IOFF sensitivity (1.42x1011). One of the main problems with current biosensors is the difficulty and expense of production in the nanoscale realm.

Ultrathin Indium Tin Oxide Accumulation Mode Electrolyte‐Gated Transistors for Bioelectronics

AbstractElectrolyte‐gated field effect transistors and electrochemical transistors have emerged as powerful components for bioelectronic sensors and biopotential recording devices. A set of parameters must be considered when developing devices to amplify weak electrophysiological signals. These include maximum transconductance values, cut‐off frequencies, and large on/off current ratios. Organic polymer‐based devices have recently dominated the field, especially when considering flexibility as a key factor. Oxide semiconductors may also offer these features, as well as advantages like higher mobility. Herein, flexible, ultrathin, indium tin oxide (ITO) electrolyte‐gated transistors are reported. These accumulation‐mode devices combine n‐type operation with µe = 9.5 cm2 Vs−1, high transconductance (gm = 44 mS), and on/off ratios (105) as well as optically transparent layouts. While oxides are normally considered brittle, mechanically flexible ITO layers are obtained by room temperature deposition of amorphous layers onto parylene C. This process results in low strain, producing devices that survive bending. ITO electrochemically degrades, however, with cycling. To overcome this, the surface is passivated with high dielectric constant inert capping layers of Ta2O5 or Ta2O5/AlN. This greatly improves stability while preserving low gate voltages. Based on their overall performance, ITO‐based EGFETs are promising for bioelectronics.

Improved Temperature-Scalable DC model for SiC power MOSFET including Quasi-Saturation effect

In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.

GaAs Cone-Shell Quantum Dots in a Lateral Electric Field: Exciton Stark-Shift, Lifetime, and Fine-Structure Splitting.

Strain-free GaAs cone-shell quantum dots have a unique shape, which allows a wide tunability of the charge-carrier probability densities by external electric and magnetic fields. Here, the influence of a lateral electric field on the optical emission is studied experimentally using simulations. The simulations predict that the electron and hole form a lateral dipole when subjected to a lateral electric field. To evaluate this prediction experimentally, we integrate the dots in a lateral gate geometry and measure the Stark-shift of the exciton energy, the exciton intensity, the radiative lifetime, and the fine-structure splitting (FSS) using single-dot photoluminescence spectroscopy. The respective gate voltage dependencies show nontrivial trends with three pronounced regimes. We assume that the respective dominant processes are charge-carrier deformation at a low gate voltage U, a vertical charge-carrier shift at medium U, and a lateral charge-carrier polarization at high U. The lateral polarization forms a dipole, which can either enhance or compensate the intrinsic FSS induced by the QD shape anisotropy, dependent on the in-plane orientation of the electric field. Furthermore, the data show that the biexciton peak can be suppressed by a lateral gate voltage, and we assume the presence of an additional vertical electric field induced by surface charges.

Integrated 1D epitaxial mirror twin boundaries for ultrascaled 2D MoS2 field-effect transistors.

In atomically thin van der Waals materials, grain boundaries-the line defects between adjacent crystal grains with tilted in-plane rotations-are omnipresent. When the tilting angles are arbitrary, the grain boundaries form inhomogeneous sublattices, giving rise to local electronic states that are not controlled. Here we report on epitaxial realizations of deterministic MoS2 mirror twin boundaries (MTBs) at which two adjoining crystals are reflection mirroring by an exactly 60° rotation by position-controlled epitaxy. We showed that these epitaxial MTBs are one-dimensionally metallic to a circuit length scale. By utilizing the ultimate one-dimensional (1D) feature (width ~0.4 nm and length up to a few tens of micrometres), we incorporated the epitaxial MTBs as a 1D gate to build integrated two-dimensional field-effect transistors (FETs). The critical role of the 1D MTB gate was verified to scale the depletion channel length down to 3.9 nm, resulting in a substantially lowered channel off-current at lower gate voltages. With that, in both individual and array FETs, we demonstrated state-of-the-art performances for low-power logics. The 1D epitaxial MTB gates in this work suggest a novel synthetic pathway for the integration of two-dimensional FETs-that are immune to high gate capacitance-towards ultimate scaling.

Investigation of optical parameters in Ge source SELBOX tunnel FET under visible spectrum

In this work, we have implemented Ge source Selective buried oxide (SELBOX) Tunnel FET for photo sensing applications in the visible range of spectrum for wavelength (λ = 300–700) nm. The various electrical parameters are extracted under dark and illumination states considering the presence and absence of trap charges at the interface of gate oxide and semiconductor. It is seen that at illumination state, the drain current degrades at low gate voltage and presence of traps lead to reduced tunnelling rate. Further, the spectral sensitivity, responsivity, and signal to noise ratio (SNR) are extracted for this TFET based photosensor with variation in λ. Result reveals that spectral sensitivity, responsivity, and signal to noise ratio (SNR) are 20.8, 0.5, and 49.5 dB, respectively, at λ = 300 nm. Further, the presence of trap charges result in degradation of these parameters. Finally, a comparative study of optical parameters with the existing data is highlighted.

Research on the Coupling Effect of NBTI and TID for FDSOI pMOSFETs.

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

In this article, a systematic investigation of negative differential resistance (NDR) on a negative capacitance Germanium source vertical TFET (NC-Ge-vTFET) is presented. The implementation and increased ferroelectric (FE) film thickness (t FE) offers a significantly high current ratio, improved subthreshold slope, high transconductance with a very low hysteresis voltage. However, NDR is exhibited and is increasingly prominent at lower gate voltage and higher t FE due to the coupling of the internal gate and drain voltages. NDR is an undesired effect in analog circuits that has to be mitigated. To suppress the impacts of NDR on the device, different approaches are carried out: varying the overlap channel thickness, gate length, drain doping and gate-drain underlap. Circuit analysis is carried out with the implementation of NC-Ge-vTFET as digital inverter. When the gate-drain underlap length is increased from 0 nm to 15 nm, the propagation delay is significantly reduced by 30.98%. Benchmarking of the proposed device has also been carried out. This renders the gate-drain underlapped NC-Ge-vTFET to be a viable candidate for high performance, nanoscale, low power digital applications.

Exploring channel length effects in 2D MoS2-Based memtransistors and their Synaptic behavior

Memtransistors, combining the functionalities of memristors and transistors, signify a substantial advancement with potential applications in areas such as neuromorphic learning and the integration of processing and memory units in current computers. Particularly, memtransistors fabricated using 2D materials have received extensive research attention due to their memory capabilities, energy efficiency, and features enabling compact integration. In this study, we examined the utilization of MoS2 monolayers grown by chemical vapor deposition (CVD), inherently imbued with defects, as memtransistors. Our focus probed into the exploration of how the change in channel length within this imperfect architectural construct exerts influences on the hysteresis loop and hence the operation of the device. In this respect, increasing the gate voltage enhanced the distinction between high and low resistance states and lengthening the channel led to a decrease in the differentiation between resistance states. Despite the shrinkage in hysteresis loop width, the memristive characteristics were preserved even at low gate voltages. Shortening the channel length widened the gap between low and high resistance states but disrupted the loop symmetry. Interestingly, relatively long channel memtransistors exhibited a more symmetrical and closer-to-ideal hysteresis. Experiments in different environments highlighted the impact of photocurrent. We applied consecutive pulses, resulting in an increase in the baseline of the current graph. Short-lived changes in the memtransistors resistance suggested its potential to simulate the short-term potentiation property of synapses. Our study on CVD grown 2D material-based memtransistors provides insights into the potential of using such defected materials in memtransistors wide usage and demonstrating their ability to emulate synaptic behavior.

Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications

In this work, a ferroelectric L-shaped tunnel FET (FE-LSTFET) is introduced to offer improvement in various DC and analog/high-frequency parameters. In this design, the incorporated FE layer enhances the vertical electric field at the source-channel interface, which improves the tunneling rate of charge carriers during the ON-state. The effect of negative capacitance (NC) and L-shaped N+ pocket causes dominance of vertical tunneling over corner tunneling (mainly at low gate voltages), which in turn reduces the transition voltage and current from 0.85 to 0.25 V and 1.2 × 10-8 to 5.67 × 10-11 A/µm respectively, thereby improving parameters such as ION, IOFF, and SSavg. Further, optimization of the thickness and doping concentration helps to keep the N+ pocket in fully depleted mode and consequently, ION/IOFF is increased from 0.3 × 1012 to 1.2 × 1014 and SSavg is reduced from 52 to 30 mV/decade. Subsequently, NC parameters such as remanent polarization (Pr) and coercive electric field (Ec) are optimized to increase the memory window, which further improves the read margin of FE-LSTFET as a memory device. Furthermore, TCAD-based simulation results show that optimizing the FE thickness improves ION and IOFF in the order of ∼ 1 and ∼ 2, respectively compared to those of C-LSTFET. With an optimum drain-overlap length, IOFF is shown to reduce from 6.6 × 10-17 to 5.43 × 10-19 A/µm due to a reduction in the SRH generation rate of the charge carriers. Despite the degradation in Cgg due to drain-overlap by the stack of FE and SiO2 layers, a significant increase in e-BTBT helps in achieving a transconductance of 2.48 × 10-4 S/µm, thus leading to a large cut-off frequency of 34.12 GHz. Next, analysis of the FE-LSTFET-based inverter shows significant improvements in several parameters including propagation delay and full swing. Moreover, FE-LSTFET shows more reluctance to self-heating effects than C-LSTFET as ION/IOFF is increased by an order of ∼ 3 at 500 K. Lastly, the performance of FE-LSTFET is benchmarked with existing TFET designs indicating that FE-LSTFET is suitable as a high-speed and low-power memory device.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit.

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60mVdec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

Characterization of larger-single-Lorentzian noise deviated from 1/f characteristics detected by a power-spectral-density-integration method

Larger-single-Lorentzian noise that deviates significantly from a 1/f characteristic generated by MOSFET is quantitatively analyzed using a unique evaluation method, which integrates power spectral density over a predetermined frequency band. As a result, the appearance of larger-single-Lorentzian noise is stochastically present and for low gate voltage. According to drain voltage dependence, it is suggested that the origin of larger-single-Lorentzian noise is in a pinch-off region and results from border traps in a gate oxide film by which hot carriers are trapped/de-trapped.

A Virtual Fabrication and High-Performance Design of 65 nm Nanocrystal Floating-Gate Transistor

Floating-gate transistor lies at the heart of many aspects of semiconductor applications such as neural networks, analog mixed-signal, neuromorphic computing, and especially in nonvolatile memories. The purpose of this paper was to design a high-performance nanocrystal floating-gate transistor in terms of a large memory window, low power, and extraordinary erasing speeds. Besides, the transistor achieves a thin thickness of the tunnel gate oxide layer. In order to obtain the high-performance design, this work proposed a set of structure parameters for the device such as the tunnel oxide layer thickness, Interpoly Dielectric (IPD), dot dimension, and dot spacing. Besides, this work was successful in the virtual fabrication process and methodology to fabricate and characterize the 65 nm nanocrystal floating-gate transistor. Regarding the results, while the fabrication process solves the limitation of the tunnel oxide layer thickness with the small value of 6 nm, the performance of the transistor has been significantly improved, such as 2.8 V of the memory window with the supply voltage of ±6 V at the control gate. In addition, the operation speeds are compatible, especially the rapid erasing speeds of 2.03 μs, 28.6 ns, and 1.6 ns when the low control gate voltages are ±9 V, ±12 V, and ±15 V, respectively.

Simulation study of multi-source hetero-junction TFET-based capacitor less 1T DRAM for low power applications

A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The analysis of the three memory functions: Write, Hold and Read of 1T DRAM has been carried out using Synopsys TCAD simulations. A storage region of Ge material is used for the accumulation of holes/to store the charge carriers. The variation in length of Ge-storage region, under lap length (Lunder), and temperature is performed to analyse the DRAM performance. In the Write operation, the tunneling window reduces to 15 nm and holes can be easily stored in the Ge-storage region. In case of Hold1 and Read1 operations, the potential barriers are reduced by 0.24 eV, and 0.1 eV respectively. In the proposed multi-source TFET with 14 nm gate length, read current ratio i.e. IR1/IR0 of 4.4, retention time (RT) greater than 10 sec, and sense margin (SM) of 1.27 × 10−6 A/µm is achieved at room temperature. The proposed multi-source TFET based 1T DRAM is operating at very low gate voltages. Therefore, this device is well suited for low power applications.

Reconfigurable Feedback Field-Effect Transistors with a Single Gate.

In this study, we present a reconfigurable feedback field-effect transistor (FET) that can operate in both p- and n-type configurations using a feedback mechanism. In contrast to previously reported reconfigurable FETs, our device utilizes a single gate to trigger a feedback mechanism at the center, resulting in steep switching characteristics. The device exhibited high symmetry of transfer characteristics, an on/off current ratio of approximately 1010, extremely low subthreshold swings, and a high on-current of approximately 1.5 mA at low gate voltages in both configurations. In addition, because of their hysteresis and bistable characteristics, they can be applied to various electronic devices. These characteristics were analyzed using a commercial device simulator.

Ionic liquid gating of YBa2Cu3O7−x with a BN capping layer for enhanced stability and efficiency

In this study, we explored the impact of ionic liquid gating on YBa2Cu3O7−x superconductivity. We observed that direct contact of YBa2Cu3O7−x and the ionic liquid N-diethyl-N-methyl-N-(2methoxyethyl)ammonium bis(trifluoromethanesulfonyl)imide (DEME-TFSI) results in irreversible electrochemical reactions, despite the application of a relatively low gate voltage at 220 K. Capping a thin layer of boron nitride (BN) on YBa2Cu3O7−x enabled a reversible modulation of carrier density at 300 K. Benefiting from the higher ion mobility of ionic liquid at 300 K, this modification led to more than a one-time increase in carrier density, a 3-time improvement in voltage modulation efficiency, and a reversible tuning of the superconducting temperature. These findings suggest that using a BN capping layer holds promise for enhancing the stability and efficiency of devices using ionic liquid gating.

Local mapping of surface potential in pentacene thin film under gate bias voltage obtained by scanning kelvin probe microscopy.

We report the local surface potential mapping of pentacene film prepared by physical vapor deposition with scanning kelvin probe microscopy where the sample is scanned under different gate voltages. Surface topography and the corresponding potential maps were obtained simultaneously. Spatial distribution of the surface potential at a low gate voltage is clearly correlated with topographic features. A lower electrostatic potential was measured at the grain boundaries (GBs), suggesting that GBs behave as hole traps. This observation is bolstered by conductive atomic force microscopy (C-AFM) data, which reveals a higher conductivity within the grains as opposed to the GBs. An increase in gate voltage minimizes the potential differences at the grain and GBs, suggesting a modification in trap occupancy. We expect that these experimental results, along with existing theories, will provide a better understanding of the microstructural-electrical properties of pentacene film. RESEARCH HIGHLIGHTS: Local surface potential mapping of pentacene film with scanning kelvin probe microscopy. Correlation between the surface potential map and topography at a low gate voltage. Decrease of the potential distribution inhomogeneity by the gate voltage increasement. Higher conductivity at inner grain than grain boundary in conductive atomic force microscopy.

Photo sensing analysis of T-shape TFET sensor under visible range of spectrum

This paper presents the optical performance of T-shape TFET based photo sensor under visible range of spectrum using a technology computer-aided design (TCAD) Synopsys simulator. The optical analysis of a photo device results in enhancement of spectral sensitivity (Sn), Signal to noise ratio (SNR), Responsivity (R), recombination rate, drain current, and optical generation rate. The result reveals that device under illumination reports magnitude of SNR are 67.79, 47.38, and 38.3 dB at λ= 300, 500, and 700 nm, respectively. The primary objective for investigating the optical operation of TFET is to detect Sn at low gate voltage and make it suitable for low power optical applications in the visible range of spectrum. Finally, a comparison table is introduced to compare the sensitivity of proposed TFET based photo sensor with the existing FET based sensor. TFET based photo sensors have found widespread applications in electronic devices such as wearable bands, smart watches, and IoT appliances, where power efficiency is critical.

Electrical properties of a low-temperature fabricated Ge-based top-gate MOSFET structure with epitaxial ferromagnetic Heusler-alloy Schottky-tunnel source and drain

We show electrical properties of a Ge-based top-gate metal-oxide-semiconductor field-effect transistor (MOSFET) structure with epitaxial ferromagnetic Heusler alloy/Ge Schottky-tunnel contacts, fabricated with a low-temperature gate-stack process. For shaping the Ge-MOSFET with the ferromagnetic source and drain (S/D) contacts, we use a combination process of Ar+ ion milling and reactive ion etching (RIE). As a consequence of the formation of a gate stack (SiO2/GeO2) using a process temperature of 240 °C, we demonstrate inversion channel MOSFETs with a low gate-voltage operation (VG ∼5 V). Furthermore, we achieve a relatively high field-effect mobility (μFE) of ∼300 cm2/Vs compared to those in a Si-based back-gate spin-MOSFET reported previously [Phys. Rev. B 102, 035305 (2020).]. This study will open a way for developing a Ge-based top-gate spin-MOSFET on the Si platform.

Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices

The effect of quantum confinement has become significant in terms of its impact on the scalability and electrostatics of ultra-thin-body double-gate MOSFETs. In this paper, we present a simplified model to account for the effect of quantum confinement, considering the contribution of the ground-state and the first excited state of the conduction band, on the electron carrier concentration, which when incorporated into the 1-D Poisson’s equation, enables the determination of the electrostatic potential. We establish the accuracy of the proposed model, over a wide range of process and electrical parameters, through aggressively benchmarking the electrostatics parameters obtained from the proposed model with results from the sp 3 d 5 tight-binding method (TBM), over a wide range of device temperatures. Furthermore, a simplified model for the integrated channel charge density is shown in the form of a diffusion layer charge where the thickness and potential of this layer, while being gate voltage dependent, enables the channel charge density obtained from the model to agree well with results from TBM. Through this physics based and accurate model for the integrated charge, a simplified understanding of the gate capacitance is shown as a series combination of the diffusion layer capacitance, strong-inversion capacitance and oxide capacitance, which includes the effects of structural confinement as well as charge confinement at low and high gate voltages, respectively.