Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications

Abstract

In this work, a ferroelectric L-shaped tunnel FET (FE-LSTFET) is introduced to offer improvement in various DC and analog/high-frequency parameters. In this design, the incorporated FE layer enhances the vertical electric field at the source-channel interface, which improves the tunneling rate of charge carriers during the ON-state. The effect of negative capacitance (NC) and L-shaped N+ pocket causes dominance of vertical tunneling over corner tunneling (mainly at low gate voltages), which in turn reduces the transition voltage and current from 0.85 to 0.25 V and 1.2 × 10-8 to 5.67 × 10-11 A/µm respectively, thereby improving parameters such as ION, IOFF, and SSavg. Further, optimization of the thickness and doping concentration helps to keep the N+ pocket in fully depleted mode and consequently, ION/IOFF is increased from 0.3 × 1012 to 1.2 × 1014 and SSavg is reduced from 52 to 30 mV/decade. Subsequently, NC parameters such as remanent polarization (Pr) and coercive electric field (Ec) are optimized to increase the memory window, which further improves the read margin of FE-LSTFET as a memory device. Furthermore, TCAD-based simulation results show that optimizing the FE thickness improves ION and IOFF in the order of ∼ 1 and ∼ 2, respectively compared to those of C-LSTFET. With an optimum drain-overlap length, IOFF is shown to reduce from 6.6 × 10-17 to 5.43 × 10-19 A/µm due to a reduction in the SRH generation rate of the charge carriers. Despite the degradation in Cgg due to drain-overlap by the stack of FE and SiO2 layers, a significant increase in e-BTBT helps in achieving a transconductance of 2.48 × 10-4 S/µm, thus leading to a large cut-off frequency of 34.12 GHz. Next, analysis of the FE-LSTFET-based inverter shows significant improvements in several parameters including propagation delay and full swing. Moreover, FE-LSTFET shows more reluctance to self-heating effects than C-LSTFET as ION/IOFF is increased by an order of ∼ 3 at 500 K. Lastly, the performance of FE-LSTFET is benchmarked with existing TFET designs indicating that FE-LSTFET is suitable as a high-speed and low-power memory device.