Low Gate Voltage Research Articles

Performance limitations of nanowire resonant-tunneling transistors with steep switching analyzed by Wigner transport simulation

We conducted a quantum transport simulation of nanowire resonant-tunneling field-effect transistors (NW-RTFETs) based on the Wigner function model. The current–voltage characteristics of the NW-RTFETs were compared with those of the nanowire transistors and nanowire resonant-tunneling diodes. For the selection of a gate with appropriate performance, symmetric and asymmetric gates with various lengths were tested, and a symmetric gate, covering the quantum well and barrier regions, was chosen as a main gate. The source-side asymmetric gates did not produce a negative differential resistance at low gate voltages in contrast to the symmetric or drain-side asymmetric gates. Although steep switching is achieved in the negative differential resistance region, the ON/OFF current ratio (ION/IOFF) is extremely low, compared to those of conventional transistors. In an attempt to increase the ION/IOFF ratio, the sizes of the semiconductor cylinder and the oxide tube were changed. This study discusses the requirements for increasing the applicability of steep switching.

Diseleno[3,2-b:2',3'-d]selenophene-Containing High-Mobility Conjugated Polymer for Organic Field-Effect Transistors.

The synthesis of a diseleno[3,2‐b:2′,3′‐d]selenophene (DSS) composed of three fused selenophenes is reported and it is used as a building block for the preparation of a high hole mobility conjugated polymer (PDSSTV). The polymer demonstrates strong intermolecular interactions even in solution, despite steric repulsion between the large Se atom in DSS and adjacent (Cβ)–H atoms which leads to a partially twisted confirmation PDSSTV. Nevertheless, 2D grazing incidence X‐ray diffraction (2D‐GIXD) analysis reveals that the polymer tends to align in a highly ordered edge‐on orientation after thermal annealing. The polymer demonstrates promising performance in a field‐effect transistor device with saturated hole mobility up to 2 cm2 V−1 s−1 obtained under relatively low gate voltages of −30 V. The ultilization of a Se‐containing fused aromatic system, therefore, appears to be a promising avenue for the development of high‐performance conjugated polymers.

Superamphiphobic Porous Structure: Design and Implementation

AbstractPorous materials with an excellent super‐repellency exist in many applications in life and industry, and their preparation is convenient and cost effective. It would be advantageous to fabricate super‐repellent porous materials. However, because of a lack of understanding of the detailed relationship between structural features and super‐repellency, it is difficult to prepare porous materials with a superamphiphobicity. Based on a theoretical analysis and the discussion of several porous structures' repellant behaviors, the criteria for fabricating super‐repellent porous materials are proposed as: (1) the most appropriate pore size being tens of micrometers to ≈100–200 µm; (2) a larger pore height; (3) a smaller porous‐network thickness; and (4) an appropriate adequate secondary microscopic structure that favors the effective pinning of a gas–liquid–solid three‐phase contact line. According to the four criteria, an optimized superamphiphobic porous material is achieved, which is a dopamine/redox graphene‐oxide‐assembled microscale porous material, which displays a super‐repellency for droplets with a surface tension of 72.8–20 mN m−1. By using the dopamine/graphene‐assembled microscale porous material, a low gate voltage (500 V) for water impaling is acquired.

Quasi-Saturated Arsenic Concentration and Uniform Electron Emission by Regulating Thermal Oxidation of Si Nanotips

The improving of tip-to-tip electron emission uniformity in an array is one of the essential issues for the vacuum microelectronic/nanoelectronic applications. Here, we report the achieving of quasi-saturated ultrahigh arsenic concentration ( $\sim 6.7\times 10^{{21}}$ /cm3) at the Si nanotip apex, in the mechanisms of dopant segregation during the thermal oxidation and the limitation of arsenic solubility in Si. The tips with quasi-saturated high-level arsenic concentration possess a well tip-to-tip uniformity in surface work function. The measured work function for the tips in an array with saturated dopant concentration is in a narrow range of 4.347–4.371 eV (~2.1% fluctuation). This merit not only resulted in high emission current density (~418.36 mA/cm2) from the devices at a relatively lower gate voltage but also brought well spatially uniform electron emission in an array. The work inspired vital insight into the interpretation for mechanisms in dopant density control and the improving of emission uniformity of the Si-tip array. It could be used as an essential approach to acquire high-performance Si-based vacuum electronic devices.

Electric Field-Controlled Magnetization in GaAs/AlGaAs Heterostructures–Chiral Organic Molecules Hybrids

We study GaAs/AlGaAs devices hosting a two-dimensional electron gas and coated with a monolayer of chiral organic molecules. We observe clear signatures of room-temperature magnetism, which is induced in these systems by applying a gate voltage. We explain this phenomenon as a consequence of the spin-polarized charges that are injected into the semiconductor through the chiral molecules. The orientation of the magnetic moment can be manipulated by low gate voltages, with a switching rate in the megahertz range. Thus, our devices implement an efficient, electric field-controlled magnetization, which has long been desired for their technical prospects.

Coupled Ion‐Gel Channel‐Width Gating and Piezotronic Interface Gating in ZnO Nanowire Devices

AbstractThe piezotronic effect has been extensively investigated and applied to the third generation of semiconductors. However, there currently is no effective method compatible with microelectronics techniques to harness the piezotronic effect. In this work, a facile and low‐energy‐consuming method to couple the channel‐width gating effect with piezotronic devices is developed by precisely patterning ion‐gel electrolyte on ZnO NW. The ultrahigh capacitance of ion gel resulting from electrical double layers allows efficient modulation of the charge carrier density in ZnO NW at low gate voltage (2 V) to compensate for the piezotronic effect. The obtained output current variation under negative gate voltage (420%, i.e., enhanced piezotronic effect) is two times higher than that under zero or positive gate biases (200%). Through quantifying the reverse‐biased Schottky barrier height and charge carrier density, it is found that the applied negative gate voltage depletes free electrons in ZnO NW and alleviates the screening effect on piezoelectric polarization charges, leading to enhanced piezotronic effect. Based on this, an ion‐gel‐gated piezotronic strain sensor is fabricated with enhanced gauge factor and tunable logic devices. It is believed that the coupled ion‐gel and piezotronic gating effect is of great significance to the design of sophisticated and practical piezotronic devices.

Temperature dependent electrical characteristics of a junction field effect transistor for cryogenic sub-attoampere charge detection

Junction field effect transistors (JFET) at cryogenic temperatures can be employed as almost perfect charge detectors with leakage currents of less than 1 aA. The electrical input and output characteristics of the commercial n-channel silicon JFET BF545B is studied as a function of temperature in the range between 30 and 300 K. As long as the charge carrier concentration is constant an increasing drain current is observed for reduced temperatures and low gate voltages. Using a constant mobility model for the device this behaviour can be explained with the higher electron mobility in the source-drain channel. The mobility is found to increase with T−1 at lower temperatures which corresponds to a dopant concentration of 7 ⋅ 1016/cm3. For larger negative gate voltages a source-drain voltage is found at which the drain current is almost temperature independent. As soon as the charge carriers freeze out the input characteristics changes significantly due to the exponential decrease of the carrier concentration. The effective reduction of the gate leakage current is crucial for ultimate sensitive charge detection. Hence, the current is measured through the entire temperature range in an open gate configuration. The leakage current decreases exponentially with lower temperatures across more than six orders of magnitude and reaches values of 10−20 A below 160 K. It is exclusively due to the generation of electron-hole pairs in the depletion layer since the data are in full agreement with the Shockley-Read-Hall model of the generation current.

Flexible Low-Voltage IGZO Thin-Film Transistors With Polymer Electret Gate Dielectrics on Paper Substrates

Polymer electret shows a good electrostatic polarization effect, resulting in very high-density charge accumulation in semiconducting channel layer at low gate voltage. In this letter, graphene oxide enhanced poly(vinyl alcohol) film was used as the gate dielectric for flexible low-voltage indium-gallium-zinc-oxide thin-film transistors (TFTs) on paper substrates. High performance with a high current ON/OFF ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 1.8\times 10^{\textsf {7}}$ </tex-math></inline-formula> , a large field-effect mobility of ~42 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> , and a low subthreshold swing of 106 mV/decade was obtained. In addition, such flexible TFTs exhibit a good stability under bending condition due to the reinforcement effect of graphene oxide. Such flexible TFTs on paper substrates have potential application in next-generation low-cost flexible paper electronics.

Charge transport mechanism in low temperature polycrystalline silicon (LTPS) thin-film transistors

Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are recently used in many display applications due to its high mobility and high stability. However, its processing at low temperature causes defects which affect charge carrier mobility. So, it is essential to completely understand the effects of defects on charge transport mechanism. In this paper, experimental results are presented to investigate the charge carrier mobility of LTPS device. Furthermore, based on the theoretical model, the charge transport characteristic for LTPS has been interpreted. Our results show that, at low gate voltage, the charge transport of LTPS TFT displays multiple trapping and release mechanism, while free charge carrier transport mechanism at high gate voltage.

Gate defined quantum dot realized in a single crystalline InSb nanosheet

A single crystalline InSb nanosheet is an emerging planar semiconductor material with potential applications in electronics, infrared optoelectronics, spintronics, and topological quantum computing. Here, we report on the realization of a quantum dot device from a single crystalline InSb nanosheet grown by molecular-beam epitaxy. The device is fabricated from the nanosheet on a Si/SiO2 substrate, and quantum dot confinement is achieved by the top gate technique. Transport measurements of the device are carried out at a low temperature in a dilution refrigerator. It is found that the measured charge stability diagram is characterized by a series of small Coulomb diamonds at high plunger gate voltages and a series of large Coulomb diamonds at low plunger gate voltages, demonstrating the formation of a gate-tunable quantum dot in the InSb nanosheet. Gate-defined planar InSb quantum dots offer a renewed platform for developing semiconductor-based quantum computation technology.

Gate Conduction Mechanisms and Lifetime Modeling of p-Gate AlGaN/GaN High-Electron-Mobility Transistors

The gate conduction mechanisms in p-gallium nitride (GaN)/AlGaN/GaN enhancement mode transistors are investigated using temperature-dependent dc gate current measurements. In each of the different gate voltage regions, a physical model is proposed and compared to experiment. At negative gate bias, Poole–Frenkel emission (PFE) occurs within the passivation dielectric from gate to source. At positive gate bias, the p-GaN/AlGaN/GaN “p-i-n” diode is in forward operation mode, and the gate current is limited by hole supply at the Schottky contact. At low gate voltages, the current is governed by thermionic emission with Schottky barrier lowering in dislocation lines. Increasing the gate voltage and temperature results in thermally assisted tunneling (TAT) across the same barrier. An improved gate process reduces the gate current in the positive gate bias region and eliminates the onset of TAT. However, at high positive gate bias, a sharp increase in current is observed originating from PFE at the metal/ p-GaN interface. Using the extracted conduction mechanisms for both devices, accurate lifetime models are constructed. The device fabricated with the novel gate process exhibits a maximum gate voltage of 7.2 V at ${t}_{\textsf {1}\%}=\textsf {10}$ years.

Comprehensive Analysis of Electrical Parameters Degradations for SiC Power MOSFETs Under Repetitive Short-Circuit Stress

The degradations of electrical parameters for silicon carbide power MOSFETs under repetitive short-circuit (SC) stress are investigated in detail in this paper. It demonstrates that the generation of negative charges along the gate–oxide interface of the channel region is the dominant degradation mechanism, which results in the increase in the threshold voltage ( ${V}_{\text {th}}$ ) and the rise of ON-state resistance ( ${R}_{\text {dson}}$ ) under low gate voltage bias condition. Furthermore, degradations of dynamic characteristics including gate charge ( ${Q}_{\text {g}}$ ) and switching behaviors of the device after the repetitive SC stress are extracted and analyzed for the first time. It illustrates that the increased ${V}_{\text {th}}$ contributes to the rise of the Miller plateau voltage ( ${V}_{\text {gp}}$ ), which further leads to the increase in gate–source charge ( ${Q}_{\text {gs}}$ ). Meanwhile, the increase in the turn-ON time and the reduction of turn-OFF time are observed, which are also resulted from the positive shifts of ${V}_{\text {th}}$ and ${V}_{\text {gp}}$ , leading to the rise of turn-ON switching energy ( ${E}_{{ \text {on}}}$ ) and the decline of turn-OFF switching energy ( ${E}_{\text {off}}$ ), respectively.

Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance

To achieve a steep subthreshold slope (SS) and a better \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio is a major concern for switching applications in semiconductor devices. To overcome these issues, the tunnel field effect transistor (TFET) is a promising device, as it has low leakage current and a low subthreshold slope at room temperature, making it a highly useful device for ultra-lower circuit applications. However, physical doping leads to random doping fluctuations, which is a serious issue in device technology. For this purpose, we report an electrically doped TFET with a metal strip implanted in the oxide layer between the channel/source junction to improve the performance of the device in terms of steep SS and \(I_\mathrm{ON}/I_\mathrm{OFF}\) at very small gate voltage. Furthermore, we have considered the appropriate length and work function of the metal strip to maintain the improved SS and \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio. The introduction of a metal strip in the oxide layer on a conventional device offers a higher \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio on the order of \(10^{8}\), steep subthreshold slope (Point \(\hbox {SS} = 8.07\) mV/decade) and significant change in analog/RF performance. The analog/RF figures of merit are observed in terms of transconductance (\(g_{m}\)), gate-to-drain capacitance (\(C_\mathrm{gd}\)), cutoff frequency (\(f_{T}\)), and gain bandwidth product. The proposed device would be very useful for ultra-low power and high frequency circuit applications at low gate voltages. All simulated results are carried out using 2-D ATLAS software.

Quasi-One-Dimensional Charge Transport Can Lead to Nonlinear Current Characteristics in Organic Field-Effect Transistors.

Nonlinearity in the current characteristics of organic field-effect transistor (OFET) devices has become a serious issue for accurate evaluation of the charge-carrier mobilities in organic semiconductors. In particular, in the case of several high-mobility materials, a kink appears in the transfer curves, and this nonlinearity has been generally interpreted as the result of poor contacts. Here, we describe another possible origin for the appearance of such a kink. Extensive molecular-scale device simulations indeed demonstrate that the quasi-1D nature of charge transport often encountered in organic crystals or highly oriented polymers can lead to significant transport through the bulk and result in nonlinearity of the transfer current characteristics if the actual charge injection is away from the channel. When this is the case, the low-gate voltage regime in fact does not overestimate the charge mobility along the channel direction.

Analysis and Modeling of Current Mismatch in Laterally Nonuniform MOSFETs

We present an analytical modeling approach for drain current ( ${I}_{D}$ ) mismatch in lateral nonuniformly doped (NUD) MOSFETs. The model uses the carrier number fluctuation theory to include the effect of random dopant fluctuations (RDFs) on inversion charge fluctuation (ICF) in different operating regions. Our analysis shows that the conventional models for uniformly doped device underestimate the ${I}_{D}$ mismatch by one-to-two orders of magnitude at low gate voltages in NUD devices. We have also considered the effect of RDF on mobility fluctuation (MF), which shows its significant role in strong inversion (SI). To investigate the physical mechanism leading to such a behavior, extensive technology computer-aided design simulations are performed for various conditions of bias, doping profiles, and temperature. Using the impedance field method to calculate the relative contributions of RDF to ICF and MF, we show that our model can successfully capture the drain current mismatch across subthreshold to SI in the NUD device.

Hybrid graphene metasurfaces for high-speed mid-infrared light modulation and single-pixel imaging

During the past decades, major advances have been made in both the generation and detection of infrared light; however, its efficient wavefront manipulation and information processing still encounter great challenges. Efficient and fast optoelectronic modulators and spatial light modulators are required for mid-infrared imaging, sensing, security screening, communication and navigation, to name a few. However, their development remains elusive, and prevailing methods reported so far have suffered from drawbacks that significantly limit their practical applications. In this study, by leveraging graphene and metasurfaces, we demonstrate a high-performance free-space mid-infrared modulator operating at gigahertz speeds, low gate voltage and room temperature. We further pixelate the hybrid graphene metasurface to form a prototype spatial light modulator for high frame rate single-pixel imaging, suggesting orders of magnitude improvement over conventional liquid crystal or micromirror-based spatial light modulators. This work opens up the possibility of exploring wavefront engineering for infrared technologies for which fast temporal and spatial modulations are indispensable.

Manipulating Doping of Organic Semiconductors by Reactive Oxygen for Field‐Effect Transistors

Thin film organic field‐effect transistors (OFETs) are usually featured with charge traps, limiting charge transport and leading to low mobility especially at low gate voltages. In this work, doping process of a model organic semiconductor 2,7‐didodecyl[1]benzothieno[3,2‐b][1]benzothiophene (C12‐BTBT) has been manipulated, using low‐cost reactive oxygen namely oxygen plasma or ozone. It is found that low‐pressure (20 Pa) oxygen plasma can induce a low‐moderate doping concentration, which is, however, sufficient to warrant field‐effect mobilities over 5 cm2 V−1 s−1 in a large gate voltage range and sharp subthreshold swings, without degradation of on/off ratio. Low‐pressure oxygen plasma can also positively shift the threshold voltage of the device, thus largely reducing the working voltages. Oxygen plasma with higher pressure than 100 Pa induces higher doping concentration, more significantly shifting the threshold voltage and deteriorating on/off ratio due to substantial bulk electrical conductivity, which is similar to the treatment by UV‐ozone at atmospheric pressure. As compared with the well‐studied organic dopant F4‐TCNQ, the doping process of reactive oxygen can be more easily in situ manipulated to reach an appropriate range of doping concentration, warranting higher performance and larger tunability for OFETs.

Investigation of the atmosphere influence on device characteristics and NO2 sensing performance of organic field-effect transistors consisting of polymer bulk heterojunction

Abstract Organic field-effect transistors (OFETs) using polymer as the active layer are being intensively developed for flexible electronics including gas sensor. The strategy of polymer blends comprising semiconducting polymer mixed into an insulating polymer matrix has shown great potential in improving the electrical and sensing performance of OFETs. Herein two semiconducting polymers of poly(3-hexylthiophene-2,5-diyl) (P3HT) and poly(9-vinylcarbazole) (PVK) are used to construct a polymer bulk heterojunction, through exploring the atmosphere influence on device characteristics and NO2 sensing performance of the transistors, an in-depth illumination of the underlying sensing mechanism is carried out. Firstly, by using nitrogen (N2) and dry air as carrier gases, the individual device characteristics and sensing performance under certain NO2 concentrations are investigated. It can be observed that O2 has a greater effect on the electrical performance than other atmospheric components, which is different from the previous report of neat P3HT-based device. Specifically, at the high gate voltage, the response of drain current under N2 is more than 2 times higher than that under dry air, and the mobility variation exhibits a 2-fold enhancement. In contrast, at a low gate voltage (0 V) under dry air, the response is 2-fold greater than under N2. Then, the underlying sensing mechanism of these gas sensors consisting of various P3HT fractions in different operating environment is discussed. Finally, the OFET gas sensor with a high sensitivity to NO2 under dry air is obtained, i.e., the highest current sensitivity is ∼12381% for 15 ppm with 50% P3HT, which is more than 30 times higher than that of pure one. This study on gas sensing mechanism of OFET consisting of semiconducting polymer bulk heterojunction can offer novel inspiration to realize high performance OFET and the corresponding gas sensor.

Vertical organic field effect transistor: on–off state definition related to ambipolar gate biasing

We investigated a vertical organic field effect transistor (VOFET) behavior with an intermediate electrode formed by a tin (Sn) layer, whose growth presents a self-organized pattern grid with natural pores, fundamental to its operation. The choose of the materials to compose the channel formed by a fullerene ( $$\text {C}_{60}$$ ) and a intermediate electrode of Sn brings a structure able to work with very low voltage and ambipolar gate biasing behavior, concomitantly. A explanation based on the importance of the roughness/pores in the intermediate electrode and the control of the energy barrier of the injection interface clarifies how to obtain the on–off state in unipolar VOFETs with ambipolar gate biasing. A theoretical basis support that when there is a low injection energy barrier inside and outside of the pores from a roughness intermediate electrode the electrical characterization its a combination of a very low voltage operation with a non negligible off-output current.

Low Substrate Temperature Modeling Outlook of Scaled n-MOSFET

Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100‒300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 𝜇m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temperature operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.