Low-power Mode Research Articles

Smart Wireless Climate Sensor Node for Indoor Comfort Quality Monitoring Application

The indoor environment climate should be controlled by continuously maintaining the temperature and relative humidity to achieve thermal comfort. A monitoring system of both parameters is the first step to improving indoor comfort quality. This paper presents a smart wireless climate sensor node for indoor temperature and humidity monitoring with a powering strategy and design approach for autonomous operation. The data logging results are sent to the cloud using Internet of Things protocol for thermal comfort monitoring and analysis. The monitoring and analysis results are useful to monitor and control the indoor thermal comfort condition for room occupants. A sensor node was designed that includes a low-power mode and compact size features. It consists of a built-in AVR-based microcontroller, a temperature and humidity sensor, and a wireless module with a supercapacitor as the power storage. A low-power algorithm and Internet of Things system were implemented to reduce the total energy consumption as low as possible during operation while improving the thermal comfort quality. This developed sensor node has a small error for temperature, and relative humidity sensed values resulting from calibration. At the same time, it also consumes low power for one cycle of data acquisition. The device was integrated with an Internet of Things monitoring system to monitor indoor thermal comfort in the field experiment. The experiment results showed that the indoor temperature and relative humidity were measured and recorded in the range of 25–30 °C and 30–40%, respectively. This prototype is a preliminary design to achieve an autonomous sensor node with a low-power energy consumption goal. Thus, with this feature, the developed sensor node has potential to couple with a micro energy harvester module toward a fully autonomous active node in further development.

Research on Pattern Extraction Method of Underwater Acoustic Signal Based on Linear Array

Underwater acoustic signal is an important reference data for marine information research. The research and application of underwater acoustic signal have been widely concerned and valued by countries and enterprises. With the needs of modern military development and the development of marine industry, the research and application of underwater acoustic signal will develop faster and faster. In order to better understand marine information, it is necessary to collect seawater acoustic signal data. Aiming at the purpose of recording underwater acoustic signals placed in the ocean for a long time, this study innovates the calibration and recording of large dynamic range of long-time underwater acoustic signals, improves the circuit setting methods such as receiving, amplification, and sampling, designs a large dynamic series of long-time underwater acoustic signal recording device, and adopts the linear array extraction method, so that it can monitor the underwater acoustic biological sound under the condition of low power. It can also monitor the blasting sound of offshore engineering. Hardware circuit design mainly includes main control chip selection, amplification circuit design, filter circuit design, analog-to-digital conversion circuit design, storage circuit design, and some auxiliary circuit design. The fourth chapter introduces the software development process of large dynamic range underwater acoustic signal recorder and mainly introduces the system development tool, system clock working method, real-time clock module working method, underwater acoustic signal acquisition method, data storage scheme design, and the use of FatFs file system. The underwater acoustic signal data is stored on a MicroSD in the form of TXT file; linear array extraction method is used for feature extraction. Compared to other methods, the transformer will suppress DC and low-frequency interference signals, thus achieving high-pass filtering characteristics. Finally, the performance and experimental results of the whole underwater acoustic signal recording device are analyzed. After testing, the underwater acoustic signal recording device designed in this paper works stably and can record underwater acoustic signals with large dynamic range for a long time in low-power mode.

A 20 Gbps PAM4 data transmitter ASIC for particle physics experiments

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 27-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

Smart-Autonomous Wireless Volatile Organic Compounds Sensor Node for Indoor Air Quality Monitoring Application.

Several studies reported the significant effect of indoor air quality on human health, safety, productivity, and comfort because most humans usually conduct 80%–90% of their activity inside the building. This is generally due to the fact that indoor pollution is associated with volatile organic compounds (VOCs), pollutants with chronic health effects, both non-carcinogenic and carcinogenic, on humans. Therefore, this study focused on developing wireless VOCs sensor nodes with a low-power strategy feature to perform an autonomous operation in indoor air quality monitoring (IAQM). The sensor node mainboard consists of a microcontroller-based AVR (ATmega-4808) that supports a low power mode and low-power IAQ-Core sensor for VOCs detection. The low-power sensing algorithm developed also allowed the sensor node to consume a total power of 0.22 mAh for one cycle of operation, which includes the initial process, TVOCs value reading process, data transmitting process, and low power mode process at a time interval of 30 min. The most significant power was observed to be consumed in the data transmitting process with 0.13 mAh or 58% of total power consumption in one cycle of sensor node operation. Furthermore, the 10F capacitance of the supercapacitor was able to drive the VOCs sensor node for 139 s and it was recommended that further studies use micro energy harvesting (from an indoor environment) to extend its lifetime. The 1541-minute field experiment conducted also showed that TVOCs and CO2 values were successfully measured and displayed over an internet connection on the monitoring terminal dashboard. The recorded real-time TVOCs value of 175 ppb (<200 ppb) indicates good air quality.

A Dual-Mode W-Band Eight-Way Parallel–Series Power-Combining PA With +18-dBm P sat and 15.1% PAE in 65-nm CMOS Technology

This letter presents the design of a Dual-mode W-band eight-way power-combining power amplifier (PA) implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology ( $f_{t}$ / $f_{{max}}$ : 210 GHz/240 GHz). A configurable parallel-series-based eight-way power combine technique is proposed to achieve high output power with high power efficiency near half of $f_{t}$ . The eight-way power-combiner is consisted of two transformer-based parallel two-way differential combiners and a coupled-line-based series combiner to achieve high passive efficiency and compact layout. The proposed PA achieves a measured peak gain of 30.9 dB with a bandwidth (BW) of 7.5 GHz. The PA has $P_{{sat}}$ of +18 dBm with an 1dB output compression point (OP1dB) of +13.8 dBm and a peak PAE of 15.1% in high-power mode. In the low-power mode (LPM), the measured $P_{{sat}}$ , OP1dB, and peak PAE are +13.6, +9.1 dBm, and 10.3%, respectively. The PAE is enhanced by 3.4% points at a 6-dB back-off in LPM. The core area of the proposed PA is 0.3 mm².

ESP32-CAM as a programmable camera research platform

Experimenting with custom-programming of cameras can be difficult. Most consumer cameras are protected to prevent users from reprogramming them. Industrial cameras can be flexibly controlled by an external computer, but are generally not stand-alone programmable devices. However, various inexpensive camera modules, designed largely to be used for building IoT (Internet of Things) devices, combine extensive programmability with a camera in a compact, low-power, module. One of the smallest and least expensive, the ESP32-CAM module, combines a 2MP Omnivision OV2640 camera with a dual-core 32-bit processor, 802.11 WiFi and BlueTooth as well as wired I/O interfaces, a microSD slot, low power modes, etc., all supported by the Arduino programming environment and a rich collection of open source libraries. Why not use it for programmable camera research? This paper describes how the ESP32-CAM had to be adapted to enable use in a variety of experimental cameras. For example, some of these cameras do not use the lens screwed and glued onto the OV2640, and replacing this lens revealed a number of issues ranging from spectral response to adjustment of lens corrections. There are numerous strange interactions between different functions that end-up sharing the same I/O pins, so work-arounds were needed. It also was necessary to devise ways to handle various higher-level issues such as implementation of a live view and synchronization across cameras. However, the key problems have been resolved with open source software and hardware designs described here.

An Experimental Evaluation of Resistive Defects and Different Testing Solutions in Low-Power Back-Biased SRAM Cells

This paper compares different types of resistive defects that may occur inside low-power SRAM cells, focusing on their impact on device operation. Notwithstanding the continuous evolution of SRAM device integration, manufacturing processes continue to be very sensitive to production faults, giving rise to defects that can be modeled as resistances, especially for devices designed to work in low-power modes. This work analyzes this type of resistive defect that may impair the device functionalities in subtle ways, depending on the defect characteristics and values that may not be directly or easily detectable by traditional test methods. We analyze each defect in terms of the possible effects inside the SRAM cell, its impact on power consumption, and provide guidelines for selecting the best test methods.

A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission

We propose a CMOS image sensor with a dedicated low-power imaging mode and low-power integrated transmitter. The proposed CMOS image sensor selectively operates in dual mode: a high-quality mode with a 1.5 V supply voltage of readout circuits to achieve a high signal-to-noise ratio (SNR), and a low-power mode with a 0.9 V supply voltage to support always-on imaging. To further reduce the power consumption in the low-power mode, a single-slope analog to digital converter (ADC) embeds a power cutoff scheme in the comparator and a two-step conversion with dual reference voltages. To alleviate the SNR degradation in the low-power mode, which inherently occurs from voltage scaling, a correlated multiple sampling technique that consumes negligible power overhead is implemented using the proposed window-counting scheme. To reduce the significant power consumption that occurs during image signal transmission, an integrated transmitter with four-stacked charge-recycling drivers is used so that four symbols are simultaneously transmitted with a shared supply voltage. A prototype CMOS image sensor with 680 × 520 pixels is fabricated using 110-nm CMOS image sensor technology. The fabricated CMOS image sensor consumes only 301 μW (at 15 fps) in the sensor core and 2.03 mW including the transmitter and phase locked loop (PLL) while generating low temporal random noise under 0.27 LSB with correlated multiple sampling.

Effect of Al2O3 Passive Layer on Stability and Doping of MoS2 Field-Effect Transistor (FET) Biosensors.

Molybdenum disulfide (MoS2) features a band gap of 1.3 eV (indirect) to 1.9 eV (direct). This tunable band gap renders MoS2 a suitable conducting channel for field-effect transistors (FETs). In addition, the highly sensitive surface potential in MoS2 layers allows the feasibility of FET applications in biosensors, where direct immobilization and detection of biological molecules are conducted in wet conditions. In this work, we report, for the first time, the degradation of chemical vapor deposition (CVD) grown MoS2 FET-based sensors in the presence of phosphate buffer and water, which caused false positive response in detection. We conclude the degradation was originated by physical delamination of MoS2 thin films from the SiO2 substrate. The problem was alleviated by coating the sensors with a 30 nm thick aluminum oxide (Al2O3) layer using atomic layer deposition technique (ALD). This passive oxide thin film not only acted as a protecting layer against the device degradation but also induced a strong n-doping onto MoS2, which permitted a facile method of detection in MoS2 FET-based sensors using a low-power mode chemiresistive I-V measurement at zero gate voltage (Vgate = 0 V). Additionally, the oxide layer provided available sites for facile functionalization with bioreceptors. As immunoreaction plays a key role in clinical diagnosis and environmental analysis, our work presented a promising application using such enhanced Al2O3-coated MoS2 chemiresistive biosensors for detection of HIgG with high sensitivity and selectivity. The biosensor was successfully applied to detect HIgG in artificial urine, a complex matrix containing organics and salts.

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> mode, a phase detector range reduction technique is used to halve the required DTC delay range (DR), resulting in lower thermal noise and better DTC linearity. Moreover, a reconfigurable dual-core voltage-controlled oscillator (VCO) provides extra freedom in power and jitter tradeoff. It achieves 83.4-fs rms jitter in fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> mode, integrated from 10 kHz to 100 MHz, with a 76.8-MHz crystal oscillator (XO) reference. In the low-power mode, the rms jitter degrades to 96.3 fs and the PLL FoM improves from &#x2212;250.1 to &#x2212;251.2 dB, as the PLL power consumption reduces from 14.2 to 8.2 mW. The measured fractional spurs are less than &#x2212;70 dBc for near-integer channels. The PLL rms jitter remains within 100 fs across the 5&#x2013;7-GHz output frequency band, thanks to the digital background calibrations. It is implemented in a 14-nm FINFET process and occupies 0.31 mm².

Impacts of Quadrature Signal Generation-Based PLLs on Low-Frequency Oscillation in an Electric Railway System

The low-frequency oscillation (LFO) issue has occurred frequently in single-phase electric train and traction network interactive systems (hereinafter train-network systems). On a single-phase electric train, the quadrature signal generation-based phase-locked loop (QSG-PLL) has been widely used to achieve unit power factor operation. The bandwidth of the single-phase PLL is close to the frequency of the LFO, but its impacts on the LFO are not considered fully in previous works. In this article, three typical QSG-PLLs are studied in depth, and their unified model is derived in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dq</i> frame. Furthermore, the impacts of the QSG-PLL structure and parameters on the LFO are revealed. The analysis results indicate that the QSG part plays an important role in the LFO analysis, but the parameters of the PLL part have slight impacts on the train’s impedance under the low-power operation mode. Three different QSGs can all be regarded as providing a second-order low-pass filter (LPF) to generate the virtual <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> component in the single-phase system. The higher damping ratio of the second-order LPF can increase the magnitude of the train’s impedance, which is beneficial to enhance the stability of the train-network system. Finally, experimental results via hardware in loop (HIL) are employed to verify the correctness of the theoretical analysis results.

Отдаленные результаты применения комбинированного лазерного лечения друзеноидной отслойки ретинального пигментного эпителия

Drusenoid pigment epithelial detachment is a condition characterized by separation of the retinal pigment epithelium from the underlying Bruch’s membrane due to formation of drusenoid deposits. The disorder represents the intermediate stage of the age-related macular degeneration, and is a risk factor for the age-related macular degeneration progression to late stage characterized by geographic atrophy, which results in the irreversible central vision loss. Management of patients with this disorder is in most cases limited to follow-up. The feasibility of using the multimodality low power mode laser therapy for treatment of drusenoid pigment epithelial detachment is reported. The results of laser photocoagulation of the retina demonstrate the morphological and functional recovery: retinal pigment epithelial detachment sealing, improvement of visual function, and restored retinal architecture.

Smart fire monitoring system for a city: design and development

All Fire Alarm Systems essentially operate on the same fundamental principle and framework. It provides audible and visual alarm signals. An alarm is raised if a sensor detects smoke or heat, warns people that there may be a fire, and evacuate the premises immediately. Consequently, concerned individuals may call the fire department to mitigate the emergency at which, at this point of time, the firefighter's Emergency Respond Time (ERT) is vital. ERT is one of the contributing factors to how much fire will consume lives and, or properties. In worst cases, an entire building turns into ashes, lives taken because of a slow ERT. Then there are these casual "false-alarms" caused by the false-positive readings of the installed Fire Alarm Systems. These false alarms cause mass panic and consume firefighters' valuable time and resources. The instances mentioned above are a few reasons why there is a need to implement an efficient city-wide fire alarm system.&#x0D; This study focused on the design, development and testing of a wide-area Smart Fire Monitoring System comprised of major parts, the devices and the system software. Specifically, this study aimed to develop a smart fire alarm device using the Agile Prototyping Methodology (APM) and employ Agile Software Development Methodology (ASDM) for the development of the Smart Fire Monitoring System Software (SFMSS). For the development of the smart fire alarm device, the proponents assembled necessary sensors, electrical components, microcontrollers, and other electrical modules to create a working smart fire alarm device that abled to detect smoke; detect temperature spikes; detect the existence of fire; broadcast a GPS coordinates to the fire department; transmit and receive data through RF signals using long-range radio frequency (RF) module and SMS technology; and, be functional and operational under Low Power mode. Concomitant with this device is its system software, SFMSS, to manage and process the broadcasted data. SFMSS is a centralized system developed for the fire department to monitor the city for a fire outbreak. SFMSS continuously communicates with the fire alarm devices to autonomously monitor fire presence via radio frequency and process SMS notifications containing GPS coordinates, convert them into a readable address, and plot it in a city map in the event of a fire emergency. The proponents conducted a Stress and Reliability Test on the smart fire alarm device and Product Evaluation for Quality, Efficiency, and Usability with the Bureau of Fire Protection Region 6 for the entirety of the system.

Decentralized Phase Shedding with Low Power Mode for Multiphase Converter

With a multiphase converter, the phase-shedding function dedicated to maximizing the power efficiency, in a manner that is dependent on the load current, is always provided by a centralized controller that induces a Single Point of Failure (SPOF). The objective of this study is to obtain a decentralized control approach to implement this function by removing any SPOF. The method consists of using identical local controllers, each associated with a converter phase, that communicate with each other in a daisy-chain structure. Instead of measuring the global output current to determine the optimal number of active phases required, each local controller measures its own leg current and takes a local decision based on threshold crossing management and inter-controller communications. Functional simulations are carried out on a 5-leg 12 V/1.2 V 60 W multiphase converter supplying a modern microcontroller. They demonstrate that the number of active phases is well adjusted, in a dynamic manner, depending on the load current level. Specific events such as load current inrush or the start-up sequence are analyzed to guarantee optimal transient responses. A maximum power efficiency tracking ability is also demonstrated. Finally, it is shown that this control strategy allows phase shedding to be implemented using as many phases as desired, in a modular manner, thereby avoiding any centralized processing.

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

Preparation of Metal Nitride Particles Using Arc Discharge in Liquid Nitrogen.

A simple process to synthesize metal nitride particles was proposed using submerged arc discharge plasma in liquid nitrogen. Gibbs standard free energy was considered for the selection of the nitride-forming materials. In this study, titanium (Ti) and aluminum (Al) electrodes were used as raw materials for nitride particle preparation. Liquid nitrogen acted as a dielectric medium as well as a nitridation source in this process. A copper electrode was also used as a non-reactive material for comparison with the reactive Ti and Al electrodes. As the operating conditions of the experiments, the arc discharge current was varied from 5 A (low-power mode) to 30 A (high-power mode). The formation of titanium nitride (TiN) and aluminum nitride (AlN) was confirmed in the particles prepared in all experimental conditions by X-ray powder diffraction (XRD). The observation using a field emission scanning electron microscope (FE-SEM) and a field emission transmission electron microscope (FE-TEM) indicated that the synthesized TiN particles showed a cubic morphology, whereas AlN particles containing unreacted Al showed a spherical morphology. The experiments using different metal electrode configurations showed that the anode generated most of the particles in this process. Based on the obtained results, a particle formation mechanism was proposed.

A PUF-based secure wake-up scheme for Internet of Things

Internet of Things (IoT) are typically powered by limited-capacity batteries. Thus, reducing energy consumption is a critical issue for the success of IoT. Recently, Wake-up Radios (WuRs) play a key role in minimizing the energy consumption by providing wake-up calls to IoT devices which are currently in a low-power sleep mode to conserve energy. On receiving a pre-defined pattern called a Wake-up Token (WuT) over the WuR, the IoT device wakes up in order to process information and/or conduct communications. However, WuR-based IoT devices are susceptible to malicious attacks, such as Denial-of-Sleep attacks designed to drain the device of its energy, or cloning attacks designed to impersonate a legitimate IoT device and perform various nefarious activities. To address these problems, the present study proposes a novel one-time wake-up token using the Physical Unclonable Function (PUF). In addition, to prevent the WuT from becoming desynchronized thereby resulting in a connection loss, a WuT resynchronization scheme is designed to maintain a constant state of synchronization between the WuTs of the gateway and the IoT devices, respectively. Finally, the proposed schemes are extended to support group wake-up and resynchronization procedures, respectively, in order to enhance the communication efficiency and improve the energy conservation. The correctness of the proposed schemes is verified through AUTLOG analysis. It has been shown that the proposed schemes are secure against various types of attacks and consume significantly less energy than existing mechanisms in waking up an IoT device.

Peak temperature analysis and optimization for pipelined hard real-time systems

This study aims to minimize the peak temperature for pipelined multi-core systems while providing hard real-time guarantees. Periodic Thermal Management (PTM) is adopted to control the temperature by periodically switching each pipelined stage into a lower power mode. The Pay-Burst-Only-Once principle from Real-Time Calculus theory is used in reverse to transform real-time guarantees into the constraints of the PTM schemes applied to all stages. We systematically study the peak temperature under PTM and present two algorithms to calculate it with different levels of accuracy and speed. A greedy principle-based heuristic method is proposed to solve the peak temperature optimization problem. Experiments are conducted on an Intel processor with physical temperature sensors. The results demonstrate that our approaches optimize the peak temperature more effectively than the sub-deadline partition approach. Simulations for scenarios involving more stages reveal that the proposed algorithms are scalable with respect to the number of stages.

Rural Healthcare IoT Architecture Based on Low-Energy LoRa.

Connected health is expected to introduce an improvement in providing healthcare and doctor-patient communication while at the same time reducing cost. Connected health would introduce an even more significant gap between healthcare quality for urban areas with physical proximity and better communication to providers and the portion of rural areas with numerous connectivity issues. We identify these challenges using user scenarios and propose LoRa based architecture for addressing these challenges. We focus on the energy management of battery-powered, affordable IoT devices for long-term operation, providing important information about the care receivers’ well-being. Using an external ultra-low-power timer, we extended the battery life in the order of tens of times, compared to relying on low power modes of the microcontroller.

A Dual-Mode InGaP/GaAs HBT Power Amplifier Using a Low-Loss Parallel Power-Combining Transformer with IMD3 Cancellation Method

A dual mode InGaP/GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) using a parallel power-combining transformer (PCT) is presented herein. A low loss transformer is implemented on a printed circuit board (PCB) to improve the passive efficiency of a PCT. Dual-mode operation is applied to reduce the current consumption at a low power level. In the low-power (LP) mode, one of the individual amplifiers is turned off to reduce the current consumption. Additionally, a third-order intermodulation distortion (IMD3) cancellation method using a PCT combiner is proposed to improve linearity performance. Nonlinear IMD3 components from each amplifier cancel each other out through magnetic coupling in the secondary winding of the PCT. The implemented PA achieves a saturated output power of 33.8 dBm and a peak power-added efficiency (PAE) of 54.5% at 0.91 GHz with a 5-V power supply. An average output power of 25.2 dBm with an adjacent channel leakage ratio (ACLR) of −42 dBc is delivered when the PA is tested with an orthogonal frequency division multiplexing (OFDM) 64-quadrature amplitude modulated (64-QAM) signal with a bandwidth of 10 MHz and peak-to-average power ratio (PAPR) of 7.8 dB. When compared with the high-power (HP) mode operation, the LP mode operation could save 48% of the current consumption at an average output power of 10.4 dBm.