An Experimental Evaluation of Resistive Defects and Different Testing Solutions in Low-Power Back-Biased SRAM Cells

Nunzio Mirabella,Matteo Sonza Reorda,Ioannis Deretzis,Antonino La Magna,Salvatore Rinaudo,Giovanna Franchino,Michelangelo Grosso

doi:10.3390/electronics11020203

Abstract

This paper compares different types of resistive defects that may occur inside low-power SRAM cells, focusing on their impact on device operation. Notwithstanding the continuous evolution of SRAM device integration, manufacturing processes continue to be very sensitive to production faults, giving rise to defects that can be modeled as resistances, especially for devices designed to work in low-power modes. This work analyzes this type of resistive defect that may impair the device functionalities in subtle ways, depending on the defect characteristics and values that may not be directly or easily detectable by traditional test methods. We analyze each defect in terms of the possible effects inside the SRAM cell, its impact on power consumption, and provide guidelines for selecting the best test methods.

Highlights

The increasing demand of low-power technologies used for most modern circuits requires more sophisticated systems than ever in terms of power consumption and reliability
Faulty vias [2,3] may be the cause of misbehavior inside the cell, especially for digital circuits; defects in the silicon die such as imperfections on gate oxide that lead to time-dependent dielectric breakdown [4] are another actual problem, which depends on the manufacturing process node, for circuits subjected to high electrical stress, causing imperfection in the system such as other kinds of manufacturing imperfections that could cause unwanted resistive connections inside the SRAM cell
The current paper further investigates additional resistive defects, including defects in symmetric positions occurring inside low-power SRAM cells, as well as in terms of power consumption and static noise margin (SNM): The effect of each resistive defect injected in the cell is evaluated and the analysis of the power consumption and SNM is performed for the assessment of non-functional faults inside the system

Summary

Introduction

The increasing demand of low-power technologies used for most modern circuits requires more sophisticated systems than ever in terms of power consumption and reliability. The MOS-channels with smaller sizes in modern node technologies involve circuits that are subject to more leakage currents than ever, especially when resistive defects lead to certain malfunction of the system For this reason, these systems implement specific methods in order to reduce power consumption in logic and memory systems [1] and this, particular methods for detecting the defects are implemented as well. In the context of the Internet of Things, devices may be required to stand in idle mode until other scheduled events or environmental changes arise Within these periods of time, it is crucial to keep the leakage current to a minimum, especially concerning SRAM cells, which may be part of large arrays and based on smaller technology nodes. Special attention is given to resistive defects inside the cell that should be detected by properly set test techniques

Results

Discussion

Conclusion