Low power SRAM cell with reduced write PDP and enhanced noise margin

Abstract

The poor noise margin (NM) and power dissipation has becomes a severe issue in scaled semiconductor device technology. The memory array is major contributors in total power consumption because the most of the time array are utilized for on-chip caches in advanced microprocessors. In this work, the novel eight transistors (8T) cell characterized to improve the read mode noise margin (RMNM), write mode noise margin (WMNM), read power delay product (PDP), write PDP and hold mode power dissipation of SRAM cell. To improve noise margin and hold power, independent read driver and storage latch merged together using stack transistor. The proposed 8T cell have moderate read mode noise performance along with 13.1% lower hold power dissipation and 18% smaller write PDP compared to existing single ended eight transistor SRAM cell at VDD =0.6V. Therefore, the proposed 8T cell could be a suitable alternative for enhanced read mode noise margin and low power SRAM design.