Low-power Low-noise Amplifier Research Articles

A fabrication of a low-power low-noise neural recording amplifier based on flipped voltage follower

In this work, a fabrication of low-voltage low-power and low-noise neural recording amplifiers are presented. An operational transconductance amplifier (OTA) was built using the flipped voltage follower (FVF). The low noise operation is achieved without increasing the bias current of the input transistors or decreasing the aspect ratio of the output transistors, which leads to large overdrive voltage.This proposed OTA is used to build a biopotential amplifier using AC coupling technique to achieve one of the lowest noise efficiency factor (NEF) of 2.13. This bioamplifier is fabricated using UMC 130 ​nm CMOS process and the measurement results are obtained. The proposed OTA is also used to design a second biopotential amplifier using active low-frequency suppression technique to achieve one of the lowest occupied area of 0.047 ​mm2 while maintaining a reasonable Noise efficiency factor (NEF) of 4.27. The active low-frequency suppression technique is used to reject the DC offset voltage while preserving high input impedance and small area. The first bioamplifier consumes 2.2 ​μA from 1 ​V supply voltage. The input-referred noise is 3.7 μVrms. The bandwidth (BW) ranges from 25 ​Hz to 9.9 ​kHz. The achieved noise efficiency factor (NEF) is 2.13. The dynamic range is 55 ​dB. It occupies a silicon area of 0.112 ​mm2. The second bioamplifier consumes 5.2 ​μW from 1 ​V supply voltage. The input-referred noise is 4.7 μVrms. The BW ranges from 110 ​Hz to 9.7 ​kHz. The achieved NEF is 4.27. It occupies an area of 0.047 ​mm2.

Design Analysis of Inductorless Active Loaded Low Power UWB LNA Using Noise Cancellation Technique

AbstractThis paper includes a design analysis of an inductorless low-power (LP) low-noise amplifier (LNA) with active load for Ultra Wide Band (UWB) applications. The proposed LNA consists of two parallel paths, one is the common source (CS) path and second is the CG path. The CG path has the edge advantage of improving overall Noise figure (NF) due to wide band impedance matching in UWB, while the CS path provides high power gain. A method for noise cancellation is adopted, to reduce the noise of CS path with the help of CG path. The proposed LNA successfully simulated in 90 nm CMOS technology. The results of proposed work indicate optimization at frequency 5.70 GHz with 3 dB bandwidth of 4.3 GHz–8.9 GHz. All simulations have been done for a range of frequency 03 GHz–13 GHz in Cadence virtuoso software. The results quoted 1.15 dB NF, −18.12 dB S11, 13.7 dB S21, maximum operating power gain (GP) 11.756 dB at frequency 5.7 GHz and available power gain (GA) is 10.17 dB at frequency 8.61 GHz, with 0.6 V, 0.92 mW broad band LNA.

A low-power low-noise multi-stage transimpedance amplifier for amperometric based blood glucose monitoring systems

In this paper, the design of low-noise, low-power transimpedance amplifier (TIA) is presented for a miniaturized amperometric based continuous blood glucose monitoring system for wearable devices. The proposed multi-stage cascode common source transimpedance amplifier circuit is designed and implemented in a 180 nm CMOS technology. It has been demonstrated that the proposed TIA shows a significant increase in transimpedance gain, 1.72 GΩ with a bandwidth of 180 kHz and input referred current noise is 18 fA/√Hz for an input current of 200 pA. The total power consumption is 52 μW with a 1.4 V supply and occupies a chip area of 110 μm × 140 μm.

A fully differential capacitively-coupled high CMRR low-power chopper amplifier for EEG dry electrodes

The use of dry electrodes is increasing rapidly. Since their impedance is high, there is a high impedance node at the connecting node between the electrode and amplifier. This leads to absorb powerline signal and high CMRR amplifiers are essential to eliminate this. In this article, we propose a low-power low-noise chopper-stabilized amplifier with high CMRR. In order to minimise the input-referred noise, an inverter-based differential amplifier is utilized. Meanwhile, a DC servo loop is designed to reject the DC offset of the electrode. Since all of the stages required a common-mode feedback, for each of the amplifiers a suitable circuit was used. Furthermore, a chopping spike filter is implemented at the final stage to attenuate the choppers’ spike. Finally, to eliminate the offset effect from the mismatch and post-layout, a DC offset rejection technique is used. The designed circuit is simulated in a standard 180 nm CMOS technology. The designed chopper amplifier consumes just 1.1 upmu hbox {W} at a 1.2 hbox {V} supply. The mid-band gain is 40 dB while the bandwidth is from 0.5 to 200 Hz. The total input-referred noise is 1 upmu hbox {V}_{mathrm{rms}} in its bandwidth. Thus the NEF and PEF of the designed circuit is 2.7 and 9.7, respectively. In order to analyse the performance of the proposed chopper amplifier against process and mismatch variation, Monte Carlo simulation is done. According to 200 Monte Carlo simulations, CMRR and PSRR are 124 dB with 6.9 dB standard deviation and 107 dB with 7.7 standard deviation, respectively. Ultimately, the total area consumption is 0.1 hbox {mm}^2 without pads.

Performance analysis of low power LNA using particle swarm optimization for wide band application

This paper characterizes a design analysis of low power (LP) and low voltage (LV) optimized low noise amplifier (LNA) for wide band applications. With review discussion on design challenges of LP and LV, a new biasing metric has been introduced for radio frequency analog circuit. The proposed LNA consists of two stages, the first stage is a current reuse topology, in which a combination of PMOS transistor stack on top of NMOS transistor has been used with series inductive peaking in the feed-back loop. It helps a lot to achieve the target of LP and LV, while the second stage is a mutually coupled CS stage, used for wideband matching to enhance the bandwidth and noise figure (NF). For optimization of passive component parameters of proposed LNA, particle swarm optimization (PSO) algorithm has been used. All the simulations have been done for a range of frequency 0–35 GHz in Cadence Virtuoso software 45-nm CMOS technology. The results quoted 18.57 dB maximum voltage gain, 2.4 dB NF, 17.1 dB S11, 16.6 dB S21, at frequency 25.4 GHz with 0.8 V, 1.6 mW broad band LNA.

Low-power ultra-wideband LNA employing CS–CD current-reuse and gain-controller resistor technique in 0.180-μm CMOS technology

In this paper, a low-power ultra-wideband low noise amplifier (LNA) is presented. The combination of dual resonance network and current-bleeding technique offers high and flat voltage gain and low noise figure (NF), and also, the gain-controller resistor technique causes better control of voltage gain to achieve flatter gain. Furthermore, the CS–CD (Common-Source Common-Drain) current-reuse technique provides output return loss reduction and eliminates buffer stage in LNA design. It has been shown that using this scheme, noticeable improvement has been obtained in the frequency range of 2–11 GHz. This improvement consists of minimum noise figure value as 2.5 dB, the maximum value of 4.2 dB and average noise figure lower than 3 dB in a wide frequency range, from 4 to 10 GHz. The proposed LNA achieves the average voltage gain of 12.35 dB with a variation of 0.85 dB in the frequency range of 2–11 GHz. Input and output return losses are below − 10 dB and IIP3 of the proposed structure is − 3 dBm. The proposed LNA consumes 9.52 mW in 1-V supply voltage. Moreover, the size of the structure is 0.54 mm2 in TSMC 180-nm technology.

A low-power low-noise amplifier with fully self-biased feedback loop structure for neural recording

This paper presents a fully self-biased, low-power LNA for neural recordings. Due to the capacitor coupling and low-supply voltage in LNA, the appropriate dc bias voltages for saturating the input transistors NMOS and PMOS of LNA should be separately provided. This paper focuses on the effects of different feedback ways to obtain input dc bias voltage, and proposes a completely self-biased structure to obtain the bias voltage directly from the inner nodes of the circuit. This connected way avoids using extra dc biasing circuit totally, saves capacitor area effectively and reduces the high-pass corner frequency greatly. Furthermore, the proposed method eliminates the likelihood for initial DC latch-up in the traditional way, making the circuit more stable. Simulated in a 0.18-µm CMOS process, the LNA consumes 1.2 µA from a 0.6 V supply, and achieves an input referred noise of 4.98 µVrms (1–10 kHz), corresponding to a noise efficiency factor of 2.13. Simulated CMRR and THD exceed 77 dB and 75 dB, separately.

A 1.7-mW −92-dBm Sensitivity Low-IF Receiver in 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS for Bluetooth LE Applications

This paper presents a 1.7-mW low-intermediate-frequency receiver design for Bluetooth low-energy (BLE) applications. The design exploits particular aspects of BLE, such as the relaxed in-band interference characteristics, more precisely the $C/I_{1~\textrm {MHz}}$ , and the relatively high-frequency-shift keying modulation index, to deliver a high level of energy efficiency and simplicity to the receiver baseband architecture. Reliable quadrature signals are generated in the RF signal path without consuming energy, which is supported by an inverter-based low-noise amplifier (LNA) that achieves high gain and low noise figure under low-power budgets. A small-signal analysis of low-power inverter-based LNAs is presented offering simple design equations. Seeking an affordable solution, the fabricated prototype is fully integrated into an earlier generation CMOS technology node ( $0.13~\mu \text{m}$ ), occupying a silicon area smaller than 0.7 mm2. The receiver achieves a sensitivity level of −92 dBm while consuming 1.41 mA from a 1.2-V supply.

A low-power low-noise CMOS bio-potential amplifier for multi-channel neural recording with active DC-rejection and current sharing

A low-power and low-noise bioamplifier for multichannel electrode arrays (MEA) is presented. Reduction in area and power is achieved (1) by means of active-integration using a small capacitor, (2) implementation of a high-pass filter without using large DC-blocking capacitors, and (3) by sharing the common parts of bioamplifiers of different channels. This bioamplifier, as the main building block of a neural recording system, has been designed to record neural signals, amplify them, filter out the unwanted signals, and extract the action potentials. Theoretical analysis on noise specification, crosstalk between the channels due to sharing parts, and power reduction has been presented and a design trade-off is achieved. Following the theoretical analysis, a 4-channel bioamplifier has been designed and simulated in 0.18 μm CMOS technology, in total layout area of 0.0976 mm2 and the current consumption of 3.2 μA per channel from ±1.2 V power supply. Based on post-layout simulation results, the power and noise specifications of the proposed design are comparable with the best specifications reported to date based on noise efficiency factor (NEF). The bioamplifier achieves a mid-band gain of 60 dB and a -3 dB bandwidth from 100 Hz to 10.2 kHz. The input-referred noise is 3.87μVrms corresponding to a NEF of 2.65, for the mentioned -3 dB bandwidth.

Low‐power switched transconductance mixer and LNA design for Wi‐Fi and WiMAX applications in 65 nm CMOS

This study proposes a wide-band low-power low-noise amplifier (LNA) and switched transconductance (SwGm) mixer. The proposed mixer is realised with a fully differential complementary metal oxide semiconductor (CMOS) SwGm configuration. It provides a high bandwidth with a low noise figure (NF) and consumes a low amount of power. Moreover, an ultra-wideband LNA is designed by using a split-load inductive technique. The combination of the LNA and the mixer has provided competitive results in terms of power, bandwidth, NF, and gain. The LNA + mixer was designed and fabricated in the 65 nm radio frequency-CMOS technology. The proposed LNA achieves 2.5 ± 0.1 dB of NF and 17 ± 1.5 dB of gain over the band of 1-10 GHz and consumes 4.8 mW of power. The proposed SwGm mixer shows a maximum conversion gain (CG) of 10 dB, a minimum NF of 10 dB, and more than -8.5 dBm of third-order input intercept point (IIP3) over the band of 10 GHz. The implemented LNA + mixer achieves 19 dB of CG, 5 dB of NF, and -6 dBm of IIP3. The on-chip LNA and mixer consume only 1.65 mW and 530 μW, respectively, from a 1.2 V supply voltage.

A 790 nW Low-Noise Instrumentation Amplifier for Bio-Sensing Based On Gm-RSC Structure

This paper presents a low-power low-noise instrumentation amplifier (IA) for bio-potential recording. The proposed IA is based on a novel Gm-RSC structure, whose gain is determined by the transconductance (Gm) and the equivalent resistance ([Formula: see text]) of the switched-capacitor (SC) load. The transconductance amplifier stage is based on the current-reuse telescope topology to achieve low noise at low-power dissipation. A resistor-controlled oscillator is designed to generate desirable operational frequency for SC load and to continuously tune the mid-band gain of the IA for different biomedical applications. Measurement results show that the input referred noise of the proposed IA is about 1.27[Formula: see text][Formula: see text]VRMS ([Formula: see text][Formula: see text]Hz) and the noise efficiency factor is 3.3. The range of tunable gain is from 28 to 40[Formula: see text]dB. The common mode rejection ratio and power supply rejection ratio at 50[Formula: see text]Hz are 72 and 78[Formula: see text]dB, respectively. The IA consumes only 660[Formula: see text]nA current at 1.2[Formula: see text]V supply and the active area of the IA is only 0.035[Formula: see text]mm2.

A low-power low-noise and high swing biopotential amplifier in 0.18 µm CMOS

In this paper, a low-power, low-noise and high swing capacitively coupled instrumentation amplifier for biomedical applications is proposed. It uses the folded cascode operational transconductance amplifier (FC-OTA) with current scaling at the output branch to reduce the noise. To overcome the reduction in the effective transconductance of the OTA due to current scaling, series–series and shunt–shunt feedback techniques are proposed at the folded node of the FC-OTA and the composite transistor is proposed at the bottom current source of the FC-OTA. An optimization procedure is also proposed for sizing the input transistors of the FC-OTA to obtain better noise-power tradeoff. To assess the efficacy of these techniques, a biopotential amplifier is designed in 0.18 µm CMOS process and it is studied through simulation. From this study, it is found that the proposed amplifier has a 1.5–22 times and 1.4 times higher input swing and output swing respectively compared to those reported in literature. It has a gain of 39.75 dB, a bandwidth of 0.3 Hz–4.4 kHz and a total input-referred noise of 3.19 µVrms integrated over 1 Hz–10 kHz. The power consumption of the amplifier is 4.07 µW at a VDD of 1.8 V. It achieves a noise efficiency factor of 2.78, and provides input and output signal swings of 14.86 mVpp, and 1.38 Vpp respectively at THD of 1%.

Analysis and Design of a Ripple Reduction Chopper Bandpass Amplifier

A low-power low-noise chopper amplifier for biosensor applications is proposed. To tackle the inherent ripple artifacts, it employs a simple ripple reduction method using a bandpass amplifier. The chopper amplifier is a linear periodic time-varying system. The method of harmonic transfer matrix is used to derive the signal and the noise harmonic transfer functions, and the theoretical results are confirmed by simulation and measurement results. Fabricated in a 130-nm standard CMOS process, the proof-of-concept prototype occupies a chip area of 0.28 mm2 and consumes $3.3~\mu {\text{A}}$ from a 1.2-V supply. The input referred noise is only 43 nV/ $({\mathrm {Hz}})^{1/2}$ .

Analysis and Demonstration of an IIP3 Improvement Technique for Low-Power RF Low-Noise Amplifiers

This paper describes a linearization method to enhance the third-order distortion performance of a subthreshold common-source cascode low-noise amplifier (LNA) without extra power consumption by using passive components. An inductor between the gate of the cascode transistor and the power supply in combination with a digitally programmable capacitor between the gate and the drain of the cascode transistor enable to improve the third-order intermodulation intercept point (IIP3) of a subthreshold LNA. The theoretical mechanisms that underlie the linearity improvement are analyzed comprehensively under the consideration of the LNA’s input stage, cascode stage, reverse isolation, and stability. A 1.8-GHz LNA was designed and fabricated using 0.11- $\mu \text{m}$ CMOS technology to prove the concept. Measurement results reveal that the linearized low-power LNA has a 14.8-dB voltage gain, a 3.7-dB noise figure, and a −3.7-dBm IIP3 with a power consumption of 0.336 mW.

Low‐noise amplifier by using a signal‐reuse wake‐up technology

A V-band low-power signal-reuse low-noise amplifier (SRLNA) implemented in 90 nm complementary metal-oxide-semiconductor technology is presented. The proposed SRLNA uses zero- V T and signal-reuse wake-up technologies to improve wake-up sensitivity and reduce power consumption. The SRLNA can be activated or turned off automatically based on the amplitude of the radio-frequency signal power. Time delays of the zero- V T envelope detector and limiting amplifier are analysed in order to loose the constraint on the maximum data-rate. Moreover, the relationship between noise figure (NF), power gain ( S 21 ), input and output return losses ( S 11 and S 22 ) of the SRLNA are discussed in detail, with the quality factors Q nf , Q I , Q in , and Q L defined for NF, S 21 , S 11 , and S 22 parameters derivations. The proposed SRLNA consumes 25 and 12 mW at activate and sleep modes, respectively. The sensitivity of the proposed SRLNA can achieve about -50 dBm.

28 nm FD-SOIプロセスにおける基板バイアスを用いた低雑音増幅器の低消費電力化

28 nm FD-SOIプロセスにおける基板バイアスを用いた低雑音増幅器の低消費電力化

A 28-GHz Low-Power Phased-Array Receiver Front-End With 360° RTPS Phase Shift Range

A low-power 28-GHz phased-array receiver (RX) front end is presented that incorporates a low-power low-noise amplifier (LNA) and a passive reflection-type phase shifter (RTPS) capable of 360° phase shift with 5-b phase resolution and low gain variation. Passive phase shifters are limited by tradeoffs between phase resolution, insertion loss, and phase shift range. The proposed RTPS load design and optimization approach leads to a 28-GHz RTPS achieving the state-of-the-art insertion loss with 360° phase shift range and low loss variation across the phase shift. The LNA adopts a transformer-coupled neutralization architecture that increases available gain, enabling lower power consumption. The phased-array front end is designed for Ka -band applications and has been implemented in 65-nm CMOS. The measured RTPS achieves 360° phase shift with 7.75 ± 0.3 dB insertion loss and an rms phase error of 0.3° at 28 GHz. The low-power phased-array RX front end has an overall gain of 9.5 ± 0.4 dB and noise figure <5.5 dB at 28 GHz. The RX front end consumes 10 mW from a 0.9-V supply with phase shifter and an LNA active area of 0.16 and 0.32 mm2, respectively, in 65-nm CMOS, demonstrating its suitability for low-power phased-array RX for emerging wireless links.

A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.

A Wide-Band High-Gain Compact SIS Receiver Utilizing a 300- $\mu$W SiGe IF LNA

Low-power low-noise amplifiers integrated with superconductor–insulator–superconductor (SIS) mixers are required to enable implementation of large-scale focal plane arrays. In this work, a 220-GHz SIS mixer has been integrated with a high-gain broad-band low-power IF amplifier into a compact receiver module. The low noise amplifier (LNA) was specifically designed to match to the SIS output impedance and contributes less than 7 K to the system noise temperature over the 4–8 GHz IF frequency range. A receiver noise temperature of 30–45 K was measured for a local oscillator frequency of 220 GHz over an IF spanning 4–8 GHz. The LNA power dissipation was only 300 $\mu$ W. To the best of the authors’ knowledge, this is the lowest power consumption reported for a high-gain wide-band LNA directly integrated with an SIS mixer.

60 GHz low‐power LNA with high g m × R out transconductor stages in 65 nm CMOS

This Letter presents a 60 GHz low power low noise amplifier (LNA) with high g m × R out transconductor stages in a 65-nm complementary metal oxide semiconductor (CMOS) technology. Different from the cascode and current-reused common source-common source (CS-CS) structure, the new transconductor proposed in this Letter comprises a CS transistor whose DC current is shared by other two transistors. With this configuration, the equivalent transconductance, g m and output resistance, R out of the transconductor are both high while its noise figure is deteriorated slightly comparing with CS structure, making it suitable for low-power LNA circuits. From the measurement results, the LNA gets a gain of 13.4 ± 1.5 dB and 3-dB bandwidth of 16.7 GHz (48-64.7 GHz). The average noise figure of the LNA is 6.1 dB with a power dissipation of 9.6 mW under 1 V power supply.