A low-power low-noise amplifier with fully self-biased feedback loop structure for neural recording

Abstract

This paper presents a fully self-biased, low-power LNA for neural recordings. Due to the capacitor coupling and low-supply voltage in LNA, the appropriate dc bias voltages for saturating the input transistors NMOS and PMOS of LNA should be separately provided. This paper focuses on the effects of different feedback ways to obtain input dc bias voltage, and proposes a completely self-biased structure to obtain the bias voltage directly from the inner nodes of the circuit. This connected way avoids using extra dc biasing circuit totally, saves capacitor area effectively and reduces the high-pass corner frequency greatly. Furthermore, the proposed method eliminates the likelihood for initial DC latch-up in the traditional way, making the circuit more stable. Simulated in a 0.18-µm CMOS process, the LNA consumes 1.2 µA from a 0.6 V supply, and achieves an input referred noise of 4.98 µVrms (1–10 kHz), corresponding to a noise efficiency factor of 2.13. Simulated CMRR and THD exceed 77 dB and 75 dB, separately.