Low-power Design Research Articles

A Low-Power High Gain and High Linearity CMOS RF Front-End Design Involving a Charge Injection Mixer for V2X Technology

In this paper, an RF front-end (RFFE) circuit consisting of a low noise amplifier (LNA) and a down-conversion mixer for vehicle-to-everything (V2X) applications in a 65-nm CMOS process is presented. V2X standard has a carrier frequency of 5.9[Formula: see text]GHz with 10 and 20[Formula: see text]MHz bandwidth options. The LNA topology of the RFFE is based on an inductively degenerated cascode common source differential approach. The mixer design uses a double-balanced topology with a charge injection method to enhance the linearity and noise figure performance. The RFFE design shows a single sideband integrated noise figure of 4.47[Formula: see text]dB with a total conversion gain of 28[Formula: see text]dB. The IIP3 is obtained as [Formula: see text]17[Formula: see text]dBm with charge injection in the mixer which is an improvement of 5[Formula: see text]dB as compared to no charge injection. The design consumes a total current of 10.24[Formula: see text]mA from a 1.2-V supply. This work is the first CMOS RFFE design implemented for V2X applications.

Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology

Low power has arisen as a chief topic in these days and hardware enterprises. Power dissipation has become a significant thought as execution and zone of VLSI Chip plan. In this paper, a design of low power for footed quasi resistance scheme in 45nanometer VLSI technology, using appropriate standard digital gates with 45nm technology, considering footed quasi resistance technique for nanoscales is introduced. Transition of logic 1 and 0 is the main problem in the cascading circuits, this problem can solved by employing a basic inverter called as Domino logic at output.Due to the precharge propagation the power dissipation is observed in domino logic, this will be resolved using PDB (Pseudo Dynamic Buffer) model. With the help of PDB nearly 67% of power saved. Even though PDB is succeeded in precharge propagation, it fails in logic transition, this may results erroneous output during cascading. With contracting technology, power utilization can decreased and over all power of the executives on chip are the critical difficulties below 100nm because of expanded intricacy. In this paper execution of low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology. In this paper we will actualize and recreate low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology.

Performance Study for Vertically Quad Gate Oxide Stacked Junction-less Nano-sheet

With technology scaling and to meet the desired design for low power and high-speed circuit, innovative design is being studied. The simulation study of vertical Quad gate oxide stacked junction-less Nano-sheet being a most promising device structure within a Nano scale regime, with the use of oxide, work function, and channel engineering for single, double, and triple fins Nano-sheet have been successfully demonstrated and implemented. From the reference model of tri-gate junction-less (TGJLFET) the structure is modified with a new design approach the with same design parameters. The First approach is by adding the fourth gate to the TGJLFET structure forms a new structure of quad gate junction-less Nano-sheet. The second approach is by extending the fins and adding source and drain pads with an underlap structure. The Third approach is adding the fin stacking and the fourth approach is adding gate oxide stacking to three fins vertical quad gate oxide stacking junction-less Nano-sheet (QGOSJLNS), all the approaches are simulated using a 3D visual TCAD environment. The improvement in the performance of the Nano-sheet device is denoted after comparing it with TGJLFET. Investigated performance includes leakage current, sub-threshold swing (SS), Drain induced barrier lowering (DIBL), threshold voltage (Vth), transconductance (Gm), the potential at core and surface fins of the Nano-sheet. Further, DC analysis of 3D QGOSJLNS an inverter is simulated and studied using 3D V-TCAD environment from Cogenda Pvt Ltd.

Low power design method of medical image display system based on FPGA

A novel low power design scheme of medical image display system is proposed, based on the research of FPGA(Field Programmable Gate Array) low power design technology and medical image display system. Firstly, the power consumption of video and image processing system based on FPGA is analyzed. Then a method to reduce the dynamic power consumption of FPGA is proposed based on the tonal and spatial characteristics of medical images. Finally, taking radiographic medical images as an example, the signal flip ratio is reduced from 37.95% to 9.68% by using software statistics, which proves that the proposed scheme can effectively reduce the dynamic power consumption of FPGA.

Comparison of lithium niobate and silicon substrate on phase shift and efficiency performance for mach-zehnder interferometer modulator

<span>In this study, the low-group velocity slow-light mach-zehnder interferometer (MZI) modulator, low loss and high efficiency for two modulator substrate lithium niobate (LN) and silicon were presented and optimized at 1.55µm operating wavelength. The high power consumption of conventional modulator was the major drawback in the operation of modulators. Therefore, it was a good time for low-power modulator design and development and to compare the LN and Silicon modulator on the phase shifted using the slow-light technique by designing the full MZI modulator consisting of splitter and combiner on both substrates. The phase shift of LN is 2% compared with the silicon 0.09% and higher phase shift give better performance with low power consumption due to the change of modulating voltage of the MZI modulator for LN while the silicon depends on modulating voltage manipulating concentration of charge carrier in doped silicon.</span>

Development Status of Smart Home System in the Era of Internet of Everything

Driven by the Internet of things technology, the development of smart home is showing a rapid and vigorous development trend. This paper mainly studies the development status of smart home system in the era of Internet of things. After a long time of operation, the system should check the power supply voltage, check whether the LCD display is normal, whether the wireless module can transmit the signal, and whether the signal collected by the sensor is normal. We check all kinds of interfaces and the circuit works normally. After running for a long time, the program checks the working condition of the chip and checks the working state of the chip. The accuracy test environment of this system is the test of air conditioner, TV and socket in the laboratory. Each command word is tested 50 times, and the number of successful experiments is recorded. The data shows that the average transmission time is about 10 ms, and 99.9% of the data transmission delay is less than 30 ms. The results show that the hardware circuit meets the requirements of low-power design, and the embedded software can reduce the system power consumption and achieve business functions through sleep wake-up mechanism.

Dual bit control low-power dynamic content addressable memory design for IoT applications

The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speedapplications. Many search engines of IoT applications require low power consumption and high-speed content addressablememory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardwaredevice used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper,a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. Theproposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match lineoutput for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design toperform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented usinga CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. Thesimulation results show that the proposed design reduces power and search delay when compared to conventional DCAMdesigns.

Low-power DSSS transmitter and its VLSI implementation

An interesting area of application in wireless data communication is direct-sequence spread spectrum (DSSS). Spread spectrum communication techniques make the signals more robust against interference and jamming. These are based on a concept that narrowband signal is scrambled before transmission in such a way that the signals occupy a much larger part of the radio frequency spectrum. As the digital and the analogue system components are required on the same substrate in today’s mixed-signal chips, the DSSS transmitter system is proposed to be implemented in field-programmable gate array (FPGA)–based platforms and application-specific integrated circuits (ASICs). With a low-power very large-scale integration (VLSI) architecture, sophisticated processing of wide-bandwidth DSSS systems can be exploited in FPGAs/ASICs. In this article, binary pseudo-noise (PN) sequences are generated using a low-power linear feedback shift register (LFSR) in order to spread transmit signals extensively. The proposed low-power design of LFSR and DSSS transmitter with implementation results is illustrated in this paper. Dynamic power dissipation of the proposed DSSS transmitter is reduced up to 15% and 15.6% when compared to the conventional LFSR and the Gold code–based systems respectively. The proposed hardware is implemented in 180-nm technology and operates at 15.36-MHz frequency.

Energy-Efficient Ultrasonic Water Level Detection System with Dual-Target Monitoring.

This study presents a developed ultrasonic water level detection (UWLD) system with an energy-efficient design and dual-target monitoring. The water level monitoring system with a non-contact sensor is one of the suitable methods since it is not directly exposed to water. In addition, a web-based monitoring system using a cloud computing platform is a well-known technique to provide real-time water level monitoring. However, the long-term stable operation of remotely communicating units is an issue for real-time water level monitoring. Therefore, this paper proposes a UWLD unit using a low-power consumption design for renewable energy harvesting (e.g., solar) by controlling the unit with dual microcontrollers (MCUs) to improve the energy efficiency of the system. In addition, dual targeting to the pavement and streamside is uniquely designed to monitor both the urban inundation and stream overflow. The real-time water level monitoring data obtained from the proposed UWLD system is analyzed with water level changing rate (WLCR) and water level index. The quantified WLCR and water level index with various sampling rates present a different sensitivity to heavy rain.

DECODING TECHNIQUE FOR LOW POWER DESIGN IN XILINX

This research paper is a survey of the current status of research and practice in various disciplines of low power VLSI developments. The paper briefly discusses the rationale of the contemporary, and concentrates on low power design, it presents the metrics and techniques that are used to access the merits of the assorted proposed for the improved energy efficiency. Power dissipation [1], [5] has become an important consideration in terms of performance and scope for VLSI chip design. The research paper describes the decoding strategies, methodology, and techniques for low power system design. Here also we have proposed the decoding technique and compared with silent coding to scale back the transition state and conserved the power which is additionally described during this research. KEYWORDS—Power minimization, decoding technique, silent coding.

Ultra low power design of multi-valued logic circuit for binary interfaces

From the dawn of the computer age, man has mass produced binary components for computers, due to which ternary or higher radix computers are not yet commercially used. It has been proved that ternary logic can be more efficient than binary logic and there are many devices in development that operate on more than two internal states. Therefore an efficient method to produce multi-valued logic on the basis of binary input provided is needed. In this article, an effective, simple, flexible, and low power consumption implementation has been proposed that can convert any binary number to a number of chosen radix. The proposed design is implemented in 32 nm TSMC CMOS. The proposed design is then evaluated in power/delay space and its performances are compared with the latest state of art designs. The proposed circuit exhibits power saving up to 92% over previous models.

A Low-Profile Autonomous Interface Circuit for Piezoelectric Micro-Power Generators

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design.

A novel ultra-low power 7T full adder design using mixed logic

The key point is to design and implementation of the full adder which provides high-speed, Power efficiency and leas area with good voltage swing”.Where the term ‘Novel’ indicates that If something is so new, genuine and original that it had never been seen, used or even thought of before, call it is considered as ‘novel’ and ‘Ultra low power’ indicates that with the minimal amount of system power is enough for performing the respective operation of its own. In this article, a new High Performance and low power full adder utilizing a distinctive design "Mixed Logic Design" is recommended in implementation. The mixed - logic design combines Modified Gate diffusion input (MGDI) Transmission Gate Logic (TGL), Static CMOS logic, Pass transistor logic(PTL )and various logics which requires the recommended circuit. Full adder is a digital circuit which performs the sum of bits. In many PC’s and various kinds of microprocessors, adders are utilized in the ALU. The traditional Complementary Metal Oxide Semiconductor (CMOS) Full adder consisting of 28-Transistors and is built on a traditional Complementary Metal Oxide Semiconductor structure. GDI technique is low power and high-speed design technique where it takes 10 T.Gate Diffusion Input is one of the circuit design logics which occupies less area, simulates with high speed and power-efficient technique. It entails less count of transistors as correlated to traditional Complementary Metal Oxide Semiconductor technology. But the disadvantage with Gate Diffusion Input technique is that it provides an output having poor logic swing after simulation. The Modified-Gate diffusion input (MGDI ) technique rectifies this issue by implementing FA with 8T.But we are implementing another alternative “Mixed logic design” (combining the GDI, CMOS, TGL, etc logics ) and designing the Circuit with least count of transistors and compare with other unique logics which helps them to simulate the circuit in a power-efficient way and time delay.

Low-power LDO Design of High-efficiency Class AB OTA Based on Adaptive Biasing

This design proposes a new low-dropout linear regulator (LDO) with low input voltage and low standby power consumption. A new type of adaptive bias circuit is proposed, which uses a high-efficiency class AB OTA based on class AB differential input stage and local common mode feedback (LCMFB), which not only increases the gain bandwidth product (GBW), but also improves current efficiency, in addition, a dynamic charging transistor (DCT) is used to enhance the transient characteristics of the circuit. The circuit design uses 0.18μm standard CMOS technology to achieve a stable output of 1.0V after the power supply voltage is adjusted from 1.2V, and the maximum output current is 100mA. The quiescent current is only 2.3μA at no-load, when the load current is converted from 1mA to 100mA within 1μs, the overcharge voltage is less than 130mV, and the full range of load current stability from 1mA to 100mA is achieved under the maximum 100pF load capacitor.

Compact model of nanometer STT-MTJ device with scale effect

The emergence and growing maturity of spintronics present new ideas and methods for low-power integrated circuit design. Spin-transfer torque magnetic tunnel junction (STT-MTJ) device is one of the spintronic candidates for future promising non-volatile memory. In this paper, a compact model for the STT-MTJ device in nanoscale is presented. By analyzing the influence of the device scale on its properties, the scale effect of the MTJ device is included. The thermal stability factor is trimmed to reflect the error rate of the scale effect of the device. Based on the compact model, the simulation is conducted with different device sizes to present the influence of the scale effect on the device characteristics, including the resistance, the critical current, the switching time, the write error rate, and other characteristics.

Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture

With the advancement in technology scaling and featuring new device design is being explored to meet the demand for low power and high-speed circuit design. Tri-gate junction-less FET (TGJLFET) is taken as a reference model in this study. The structure of the reference model is modified to arrive at three different device structures; the first one with two dielectric materials for gate oxide, the second one with three dielectric materials, and the third with three dielectric materials with Rectangular Core–shell (RCS) Architecture having opposite doping at the center of the channel. The performance of these three new structures was evaluated and compared with one another and also with the reference model structure. Investigated performance parameters include leakage current, sub-threshold swing, Drain induced barrier lowering (DIBL), threshold voltage, transconductance (Gm), Output Conductance (Gd), Early Voltage (Ve), Intrinsic Gain (Av), the potential at core and surface fin of the Tri-gate device. The simulation results reveal that the device with gate trioxide with RCS Architecture shows good performance with respect to the above parameters when compared with the two new device structures and reference model. Further, an inverter is simulated using TGJLFET trioxide with RCS Architecture and its DC analysis and signal to noise margin were studied. For all the simulations 3D visual TCAD device simulator from Cogenda Pvt Ltd is used.

A Novel Efficient CNFET-Based Inexact Full Adder Design for Image Processing Applications

Employing inexact arithmetic circuits in error-resilient applications results in reduction of hardware-level metrics such as power consumption, delay and occupied area. These criteria are very important in portable applications because they are battery limited. Full Adder cell is as a building block of many arithmetic circuits. Therefore, it can influence the performance of the entire digital system. This paper presents a novel low-power and high-speed design of one-bit inexact full adder cell based on 32-nm (CNFET) technology for error resilient applications. This design technique can be utilized in various applications particularly in image processing. The presented design employs capacitive threshold logic (CTL) approach which significantly reduces the number of transistors. The peak signal-to-noise ratio (PSNR) is considered to evaluate accuracy of circuits at application level. Then extensive simulations regarding various power supplies, temperatures and loads at transistor level are performed to measure power consumption and propagation delay criteria. Moreover, some new metrics are introduced to trade-off between application and hardware level parameters. Comprehensive simulations demonstrate the supremacy of the proposed cell than others.

Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

Reconfigurable TPM Implemented with Ultralow-Power Management in 28nm CMOS Process for IoT SoC Design

There have been amazing developments in the security applications of sensors for Internet of Things (IoT), which lead to the increasing demand for the System-on-a-Chip (SoC) based on Trusted Platform Module (TPM). Low-power design has become the key to enhancing the competitiveness of IoT’s product. The reconfigurable design can effectively reduce power consumption under the condition of ensuring the performance of the system. In this paper, a reconfigurable TPM with a power management module using 28nm CMOS process is proposed, which guarantees the energy saving and effectiveness of the chip. By integrating clock management, power management and multi-voltage management strategy, the designed TPM power management unit achieved a dynamic power reduction level of $$72.61\%$$ , a leakage power reduction level of $$82.05\%$$ and a total power reduction of $$72.68\%$$ with the combination of reconfigurable TPM chips without ultralow-power management.

Design of a triple pocket multi-gate material TFET structure for low-power applications

In this paper we propose a triple-pocket multi-gate material TFET (TP-TFET) device structure for a low-power and high-performance circuit design. The proposed device structure integrates the good features of both the conventional MOSFET and tunnel FET. This is achieved through three doped pockets and dual work-function gate material on near the source–channel junction. In the proposed device, the ON state conduction mechanism is dominated by an over-the-barrier thermal diffusion of carriers, thereby offering a high-value drive current. On the other hand, the subthreshold conduction mechanism is dominated by the tunnelling of carriers, thereby incurring a very small leakage current and offering a small subthreshold slope. We use 2D TCAD device simulations for the analysis of the TP-TFET and its comparison with the existing pocketed-heterogate TFET (PHG-TFET). We observe that the proposed TFET offers the average subthreshold slope (SSavg) of 2.85 mV dec−1 and ON current of ∼230 µA µm−1 as compared to the existing PHG-TFET, which offers SSavg of 44.91 mV dec−1 and I ON = ∼62 µA µm−1. Further, some benchmark circuits are implemented using these devices. A ring oscillator designed using the TP-TFET shows approximately a 6× higher frequency as compared to that designed using the PHG-TFET. The power delay product of the NAND gate and NOR gate obtained using these devices differ by approximately 3× to 20× as the supply voltage is decreased from 1.0 to 0.5 V.