Performance Study for Vertically Quad Gate Oxide Stacked Junction-less Nano-sheet

Abstract

With technology scaling and to meet the desired design for low power and high-speed circuit, innovative design is being studied. The simulation study of vertical Quad gate oxide stacked junction-less Nano-sheet being a most promising device structure within a Nano scale regime, with the use of oxide, work function, and channel engineering for single, double, and triple fins Nano-sheet have been successfully demonstrated and implemented. From the reference model of tri-gate junction-less (TGJLFET) the structure is modified with a new design approach the with same design parameters. The First approach is by adding the fourth gate to the TGJLFET structure forms a new structure of quad gate junction-less Nano-sheet. The second approach is by extending the fins and adding source and drain pads with an underlap structure. The Third approach is adding the fin stacking and the fourth approach is adding gate oxide stacking to three fins vertical quad gate oxide stacking junction-less Nano-sheet (QGOSJLNS), all the approaches are simulated using a 3D visual TCAD environment. The improvement in the performance of the Nano-sheet device is denoted after comparing it with TGJLFET. Investigated performance includes leakage current, sub-threshold swing (SS), Drain induced barrier lowering (DIBL), threshold voltage (Vth), transconductance (Gm), the potential at core and surface fins of the Nano-sheet. Further, DC analysis of 3D QGOSJLNS an inverter is simulated and studied using 3D V-TCAD environment from Cogenda Pvt Ltd.