Low Drain Bias Research Articles

Degradation Under Low Drain Bias Induced by Heavy Ion in SiC MOSFETs

Degradation Under Low Drain Bias Induced by Heavy Ion in SiC MOSFETs

Investigation of the Trapping and Detrapping Behavior by the On-State Resistance at Low Off-State Drain Bias in Schottky p-GaN Gate HEMTs

GaN power HEMTs enable the design of power electronic systems with highest efficiencies and reduced size. Despite strong advancements in device reliability, charge carrier trapping is still an important challenge. The applied methodology allows to characterize defects that cause the dynamic RDS,on in GaN power devices at product level with flexibility in duty cycle, number of pulses and mission profile. A pronounced trapping is observed for lateral GaN-on-Si HEMTs with Schottky p-GaN gate structure at low drain bias and long off-state pulses (> 100 ms). The effect is investigated by fast determination of the on-state resistance RDS,on under different trap capturing conditions: a) different drain bias b) off-state time and number of cycles c) variation of temperature. The trapping and detrapping effects are characterized and the activation energy is extracted from time constants. An elevated on-state resistance was present for up to 3 hours. The threshold voltage modification due to high drain bias does explain the significant RDS,on increase.

Characteristics of Fully-Depleted Poly-Si Thin Film Transistors Operated in Above-Threshold Region with Low Drain Bias

Transfer and output characteristics of fully-depleted polycrystalline silicon thin film transistors, including both tail and deep acceptor-like trap states in bulk, in the above-threshold region with low drain bias are presented under low or high state density in the situation without or with interface charge, respectively. The characteristics are calculated by a simple surface-potential-based drain current model in the strong inversion region with valid bias condition explained, and 2D-device simulation. The above-threshold region is found to be divided into Regions I and II, with Vsi , indicating the channel beginning to be completely strongly-inverted and large currents, and explication of deviations between the model and simulation in Region I. The large-traps effect on the range of Region I and Vth in the high state density situation is discovered.

On short channel effects in high voltage JFETs: A theoretical analysis

In this work, the impact of Short Channel Effects (SCEs), particularly Drain Induced Barrier Lowering (DIBL) on the performance of a high voltage Silicon Carbide (SiC) JFET has been thoroughly investigated. Drift-Diffusion simulations of on-state current-voltage characteristics and breakdown performance have been completed for different gate junction depths (xj) and mesa widths (MW). Due to the short channel length, realistic implant doping profiles extracted from experimentally calibrated Monte-Carlo based SRIM simulations have been used. Two suitable designs to eliminate premature DIBL-induced failure have been found: xj = 0.7 µm for MW=1.75 µm, and xj = 1 µm for MW=2 µm. We found that a 0.3 µm junction depth has a breakdown voltage of only 50 V due to collapse of the source-drain barrier at a relatively low drain bias. Threshold voltage (Vth) decreases with increasing junction depth, approaching 0 V. This is due to a combination of greater lateral straggling of implanted ions and improved electrostatic control of the channel. Our calculations demonstrate that the most robust option to mitigate DIBL and consequently early breakdown is to maintain xj≥1 µm. At this depth, the threshold voltage has a weak dependence on drain bias, indicating diminishing SCEs. Decreasing the mesa width mitigates early breakdown but requires a mesa width of less than 1.75 µm, which poses fabrication challenges.

Comprehensive High-Voltage Parameter Extraction Strategy for BSIM-BULK HV Model

In this work, parameter extraction methodology for the BSIM industry standard high-voltage (HV) device compact model is presented. An extraction procedure covers entire range of operation, including weak inversion to strong inversion region, low and high drain biases, and multiple body biases with temperature effects. The extraction procedure is validated with experimental and numerical simulation data for several configurations of HV devices, including geometric variations.

Electric‐Dipole Gated Two Terminal Phototransistor for Charge‐Coupled Device

AbstractThe demand for charge‐coupled device (CCD) imagers has surged exponentially during the last decade owing to their exceptionally high quality and low noise imaging. However, they are still confronting the performance constraints of high operation power, low speed, and limited charge integration. Here, the electric‐dipole gated phototransistor operation without external gate bias is reported by using high‐k HfO2 dielectric material. The electrostatic coupling of photogenerated charges from the Si with the graphene channel through a 10 nm HfO2 layer is demonstrated. The device exhibits remarkable performance in the broadband spectrum (266–1342 nm) at low drain bias voltage. The high values of responsivity, external quantum efficiency, and detectivity of 3.7 × 103 A W−1, 0.72 × 104, and 6.20 × 1013 cmHz½ W−1, respectively, for 800 nm wavelength and 3.3 × 103 A W−1, 1.31 × 104, and 5.61 × 1013 cmHz½ W−1, respectively, for 400 nm wavelength without gate are achieved. This discovery may potentially eliminate the requirement for gate terminals from commercial CCD devices. The power efficient features of this gateless image sensor can be fabricated at the industrial scale for the future machine vision market.

Heavy-ion induced gate damage and thermal destruction in double-trench SiC MOSFETs

This article presents the experimental results of the heavy-ion-induced gate oxide damage and single-event burnout (SEB) in 1200 V SiC double-trench MOSFETs. The short-circuit between any two terminals of devices under test (DUTs) was observed during the exposure with a drain bias of only 100 V and post-irradiation measurements. In addition, the experimental results also showed that the SEB threshold of DUTs does not exceed 500 V, which was lower than 42 % of the rated breakdown voltage. TCAD simulations revealed that the electric field concentrated at the corner and sidewall of gate oxide, resulting in the latent oxide damage, which should be responsible for the leakage current degradation at low drain bias. It was also verified that the SEB failure was due to the thermal destruction caused by the high temperature near the n− drift/n+ substrate junction, which was further determined by the SEM image of the die surface. The findings in this article could provide indications for future use of such state-of-the-art SiC double-trench MOSFETs in space.

Low-Temperature Characteristics of Nanowire Network Demultiplexer for Qubit Biasing.

In current quantum computers, most qubit control electronics are connected to the qubit chip inside the cryostat by cables at room temperature. This poses a challenge when scaling the quantum chip to an increasing number of qubits. We present a lateral nanowire network 1-to-4 demultiplexer design fabricated by selective area grown InGaAs on InP, suitable for on chip routing of DC current for qubit biasing. We have characterized the device at cryogenic temperatures, and at 40 mK the device exhibits a minimum inverse subthreshold slope of 2 mV/dec, which is encouraging for low power operation. At low drain bias, the transmission breaks up into several resonance peaks due to a rough conduction band edge; this is qualitatively explained by a simple model based on a 1D real space tight-binding nonequilibrium Green’s functions model.

Impact of heavy-ion irradiation on gate oxide reliability of silicon carbide power MOSFET

SiC power MOSFETs were exposed to 79Br, 64Cu, and 47Ti ions with different biases. After irradiation, the static parameters of the device did not change significantly. The oxide reliability is also not affected after ON-state irradiation. However, noticeable degradation of gate oxide reliability has been found after heavy-ion exposure with extremely low drain bias(50 V). The degradation is attributed to defects in the gate oxide. According to the analysis of the experimental results, the defects are caused by the high electric field induced by the partial SEGR effect during heavy-ion irradiation.

Paving the Way for Tunable Graphene Plasmonic THz Amplifiers

This study reviews recent advances in room-temperature coherent amplification of terahertz (THz) radiation in graphene, electrically driven by a dry cell battery. Our study explores THz light–plasmon coupling, light absorption, and amplification using a current-driven graphene-based system because of its excellent room temperature electrical and optical properties. An efficient method to exploit graphene Dirac plasmons (GDPs) for light generation and amplification is introduced. This approach is based on current-driven excitation of the GDPs in a dual-grating-gate high-mobility graphene channel field-effect transistor (DGG-GFET) structure. The temporal response of the DGG-GFETs to the polarization-managed incident THz pulsation is experimentally observed by using THz time-domain spectroscopy. Their Fourier spectra of the transmitted temporal waveform through the GDPs reveals the device functions 1) resonant absorption at low drain bias voltages below the first threshold level, 2) perfect transparency between the first and the second threshold drain bias levels, and 3) resonant amplification beyond the second threshold drain bias voltage. The maximal gain of 9% is obtained by a monolayer graphene at room temperatures, which is four times higher than the quantum limit that is given when THz photons directly interact with electrons. The results pave the way toward tunable graphene plasmonic THz amplifiers.

Noise immune dielectric modulated dual trench transparent gate engineered MOSFET as a label free biosensor: proposal and investigation.

We propose and investigate a biosensor based on a transparent dielectric-modulated dual-trench gate-engineered metal–oxide–semiconductor field-effect transistor (DM DT GE-MOSFET) for label-free detection of biomolecules with enhanced sensitivity and efficiency. Various sensing parameters such as the ION/IOFF ratio and the threshold voltage shift are evaluated as metrics to validate the proposed sensing device. Additionally, SVth (the Vth sensitivity) is also analyzed, considering both positively and negatively charged biomolecules. In addition, radiofrequency (RF) sensing parameters such as the transconductance gain and the cutoff frequency are taken into account to provide further insight into the sensitivity of the proposed device. Furthermore, the linearity, distortion, and noise immunity of the device are evaluated to confirm the overall performance of the biosensor at high (GHz) frequency. The results indicate that the proposed biosensor exhibits a SVth value of 0.68 for positively charged biomolecules at a very low drain bias of 0.2 V. The proposed device can thus be used as an alternative to conventional FET-based biosensors.

An Above Threshold Model for Short-Channel DG MOSFETs

An above-threshold I-V model is developed for short-channel double-gate (DG) MOSFETs. It is a non-gradual channel approximation (non-GCA) model that takes into account the contribution to carrier density from the encroachment of source-drain bands into the channel. At low-drain bias voltages, the effect appears as a gate-voltage-dependent reduction of channel resistance, with stronger effects at low gate overdrives. At high-drain biases, the intersection of source band encroachment with the gate-controlled channel potential leads to a point of virtual cathode a small distance from the source. By incorporating the depletion of carriers in the source and drain regions into the boundary conditions, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ds</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> characteristics generated by the model are shown to be consistent with TCAD simulations.

The Extraction of Polyoxometalate Flash Compact Model and Corresponding Circuit Simulation

The main component of the POM flash memories is a polyoxometalates (POMs) layer which is used as the floating gate. As a competitive candidate of NAND Flash, POM flash memories attract significant interest and intensive investigations which have been conducted on modelling its physical characteristics and electrical properties. In this paper, we report the development of a specific compact model extraction strategy for POM flash memory based on BSIM4 compact model, allowing the corresponding circuit performance investigation. POM flash compact models are extracted and optimized using genetic algorithm (GA) at the three POM flash redox states. The extracted models are in good agreement with both high drain and low drain bias TCAD simulations. For the first time, the extracted compact models are applied in the circuit simulation to investigate the circuit behaviour of POM flash cells. This will provide valuable guidance for the practical design using POM flash cells.

Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap.

Influence of temperature and dimension in a 4H-SiC vertical power MOSFET

A study of the impact of dimension and temperature on a state of the art 4H-SiC power vertical DMOSFET has been carried out using drift-diffusion calculations in conjunction with electrical characterizations to extract physical parameters and doping profiles in a 6 μm channel length device. The model presented in this paper includes the effect of trapping in the channel/oxide interface. Using these parameters, the performance of corresponding lateral and vertical scaled devices are studied. Electrothermal simulations showing self-heating effects are also carried out. The results are qualitatively discussed with the help of an analytical physical model, which considers the interplay between the different device resistances. At low drain bias, the drain current is increased by 42.86% (I D = 5 A at V G = 20 V) when reducing the dimension vertically, whereas it is decreased by 28.57% (I D = 2.5 A at V G = 20 V) when reducing the dimension laterally. These effects are enhanced at high drain bias. In addition, the effect of dimension reduction for breakdown voltage, electric field and impact ionization is investigated. A substantial reduction in breakdown voltage was found when the vertical dimensions were decreased as compared to the lateral dimensions.

Heavy-Ion Microbeam Studies of Single-Event Leakage Current Mechanism in SiC VD-MOSFETs

Heavy-ion microbeams are employed for probing the radiation-sensitive regions in commercial silicon carbide (SiC) vertical double-diffused power (VD)-MOSFETs with micrometer accuracy. By scanning the beam spot over the die, a spatial periodicity was observed in the leakage current degradation, reflecting the striped structure of the power MOSFET investigated. Two different mechanisms were observed for degradation. At low drain bias (gate and source grounded), only the gate-oxide (at the JFET or neck region) is contributing in the ion-induced leakage current. For exposures at drain-source bias voltages higher than a specific threshold, additional higher drain leakage current is observed in the p-n junction region. This provides useful insights into the understanding of basic phenomena of single-event effects in SiC power devices.

A 0.7-mW V-Band Transformer-Based Positive- Feedback Receiver Front-End in a 65-nm CMOS

In this letter, we propose an ultralow-power transformer-based V-band receiver front-end using a 65-nm CMOS technology. Forward-body-bias and transformer-based positive-feedback topologies are utilized to enable its operation at a low drain bias of 0.3 V, while still ensuring its gain performance. A resistive ring mixer, with its advantage of zero-dc-power consumption, serves as the frequency down-converter of the system. The proposed receiver front-end demonstrates an 8.5-dB conversion gain and possesses the power-saving ability to use only 0.7 mW of dc-power consumption.

Study on the Nonlinear Output Characteristic of Tunnel Field-effect Transistor

This paper investigates the output characteristics in tunnel field-effect transistor (TFET). The nonlinear current (NLC) in output characteristics has remained as a critical issue for operating at low drain bias (VSUBDS/SUB). In this paper, the energy band diagrams and charge density distributions are analyzed to confirm the relation between output current and VSUBDS/SUB, based on the technology computer-aided design (TCAD) simulations. Then, the NLC is analyzed as a channel potential pinning which occurs from the charges supplied from the drain to the channel.

COFs Meet Graphene Nanoribbons

2D covalent organic frameworks (COFs) have received considerable attention because of their crystallinity, permanent porosity, and tunability, yet they exhibit low in-plane conductivity. In this issue of Chem, Fischer and co-workers report an approach for growing 2D COF thin films featuring high in-plane conductivity for potential use in organic electronics.

Origin of Off‐State Current in Multilayered MoTe2 Field‐Effect Transistors: Gate‐Induced Drain Leakage and Poole–Frenkel Conduction

Herein, as one of bias‐dependent channel leakage issues in p‐channel multilayered molybdenum ditelluride field‐effect transistors (m‐MoTe2 FETs), anomalous increase in off‐state current is reproducibly observed with increase in drain‐to‐gate voltage (VDG), even after hydrophobic, cyclic transparent optical polymer (CYTOP) encapsulation. For elucidation on the behind mechanism for the phenomena, drain‐ and gate‐bias dependent channel leakage currents are systematically analyzed in the range of temperature 100 to 380 K. Surprisingly, analysis on trap‐assisted indirect tunneling current substantiates that the off‐state current is mainly attributed to gate‐induced drain leakage (GIDL) current associated with band bending in m‐MoTe2 FETs. Moreover, linear slope (0.00163) of ln (IDS/F) versus F1/2 plot and its coincidence with theoretical value (0.00148) identify that thermal emission associated with Poole–Frenkel effect is strongly involved at low drain bias of −1.1 V (e.g., effective barrier height, ϕB ≈ 0.61 eV), whereas GIDL current becomes more predominant at high drain bias of −3.1 V (ϕB ≈ 0.51 eV). Thus, in‐depth understanding on the origin of anomalous leakage current and its systematic validation would be beneficial for the development of novel devices and circuits based on transition metal chalcogenides (TMDCs).