Low Drain Bias Research Articles

Sharp-switching band-modulation back-gated devices in advanced FDSOI technology

A band-modulation device with a free top surface, named Z3-FET (Zero front-gate, Zero swing slope and Zero impact ionization) and fabricated in the most advanced Fully Depleted Silicon-On-Insulator technology, is demonstrated experimentally. Since the device has no front gate, the operation mechanism is controlled by two adjacent heavily doped buried ground planes acting as back-gates. Characteristics such as sharp quasi-vertical switching, low leakage, and tunable trigger voltage are measured and discussed. We explore several variants (thin and thick silicon or SiGe body) and show promising results in terms of high current, switching performance and ESD capability with relatively low back-gate and drain bias operation.

Impact of phonon scattering in Si/GaAs/InGaAs nanowires and FinFets: a NEGF perspective

This paper reviews our previous theoretical studies and gives further insight into phonon scattering in 3D small nanotransistors using non-equilibrium Green function methodology. The focus is on very small gate-all-around nanowires with Si, GaAs or InGaAs cores. We have calculated phonon-limited mobility and transfer characteristics for a variety of cross-sections at low and high drain bias. The nanowire cross-sectional area is shown to have a significant impact on the phonon-limited mobility and on the current reduction. In a study of narrow Si nanowires we have examined the spatially resolved power dissipation and the validity of Joule's law. Our results show that only a fraction of the power is dissipated inside the drain region even for a relatively large simulated length extension (approximately 30 nm). When considering large source regions in the simulation domain, at low gate bias, a slight cooling of the source is observed. We have also studied the impact of the real part of phonon scattering self-energy on a narrow nanowire transistor. This real part is usually neglected in nanotransistor simulation, whereas we compute its impact on current---voltage characteristic and mobility. At low gate bias, the imaginary part strongly underestimated the current and the mobility by 50 %. At high gate bias, the two mobilities are similar and the effect on the current is negligible.

Study of temperature variation on threshold voltage and sub-threshold slope of E $$\delta$$ δ DC MOS transistor including quantum corrections and reduction techniques

For low power System-on-Chip applications, where cost is a critical factor, recently proposed epitaxial delta doped channel (E\(\delta\)DC) structure is a promising alternative architecture within the planar bulk MOS transistor technology due to enhanced electrostatic integrity and reduced threshold voltage variability Sengupta and Pandit (IEEE Trans Electron Dev 63(2):551–557, 2016). In this paper we present a comprehensive analytical and technology computer-aided design (TCAD) simulation study of the effects of variation of temperature on the threshold voltage and sub-threshold slope of an n-type E\(\delta\)DC MOS transistor in the wide range of 100–500 K. We assume Berkeley Short Channel IGFET Model (BSIM) framework for the analytical model. The quantum correction of the threshold voltage is considered while developing the analytical model. The amount of short channel effects at low and high drain bias increase linearly with temperature above 300 K and reduces with reduction in temperature below 300 K. The sub-threshold slope varies linearly with temperature. Another important contribution of this work is that, we also discuss two strategies for reducing the effect of temperature variations on the threshold voltage at the device design level and at the circuit design level.

Comparison of phonon scattering in nanowire field effect transistors with Si, GaAs and InGaAs cores using the NEGF formalism

Using the Non-equilibrium Green's Function (NEGF) formalism, the impact of electron- phonon scattering on the performance of different core nanowire field effect transistors (NWFETs) has been investigated. Three core materials have been considered: Si, GaAs and InGaAs. The effective mass approximation has been used, with masses extracted from tight- binding simulations. The ID-VG characteristics at low and high drain bias are shown. It was found that at low drain bias, scattering caused a 86%, 72% and 50% percentage reduction in the current at high gate bias in the Si, GaAs and InGaAs core, 2.2 × 2.2 nm2 cross-section NWFETs respectively. The phonon-limited mobility and percentage tunnelling have also been calculated.

Germanium Junctionless MOSFET with Steep Subthreshold Swing

Over the past few decades, the classical Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has undergone aggressive scaling, and ultimately reached its scaling limits due to inherent short channel effects, random dopant fluctuations and increased parasitics [1]. The downscaling is foreseen to continue with multiple gate structures, but at the expense of increased parasitics and challenges in steep source/drain junctions. The Junctionless (JL) multiple gate MOSFET, overcomes these limitations as it does not require any pnjunction and is easy to fabricate [2]. Apart from the potential for low power logic, analog and RF applications, JL MOSFETs exhibit steeper Subthreshold Swing (S-swing) due to impact ionization phenomena at relatively lower drain voltages in comparison to conventional inversion mode transistors [3]. The steep S-swing for symmetric gate operation in silicon Double Gate (JL) was obtained at a drain bias (V ds) of 2 V. A possible option to reduce the V dsrequired to trigger impact ionization is to use a lower bandgap material such as Germanium (Ge), which is also considered as strong candidate for future devices due to higher carrier mobility. In this work, Ge JL Double Gate (DG) n-channel MOSFETs (figure 1) have been studied using ATLAS simulation tool [4]. Our simulation results, published earlier [5-6], for silicon JL MOSFETs depicting steep S-swing, hysteresis, increase in the number of decades of drain current transition with applied drain bias are in good qualitative agreement with the experimental results on silicon JL transistors [3]. In this work, we focus on Ge JL transistors and analyze the impact of impact ionization for achieving steep S-swing values at low drain bias. Our results (figure 2) show an impact ionization triggered steep transition in the subthreshold current with an ideal S-swing (< 1 mV/decade) at a drain bias of 1.3V. The phenomenon of impact ionization in Ge JL MOSFETs is analyzed in terms of Generation-Recombination (G-R) rates and the product of current density and electric field (J.E). Results show that a current transition of nearly 3.5 is achieve in Ge JL MOSFETs at the onset of steep S-swing while the same is limited an order in Si JL transistors. Ge based devices also exhibit a higher value of (J.E) which is directly correlated with the higher degree of impact ionization in the device. The work demonstrates new opportunities for achieving steep subthreshold swing at relatively lower drain voltages in emerging technologies. Acknowledgement: This work is supported in part by University Grants Commission, Government of India, through the Junior Research Fellowship (JRF) award to Manish Gupta (Ref.: 4015/NET-June2013), and in part by the Science and Engineering Research Board, Department of Science and Technology, Government of India, under Grant SR/S3/EECS/0130/2011.

Non-equilibrium Green's functions study of discrete dopants variability on an ultra-scaled FinFET

In this paper, we study the effect of random discrete dopants on the performance of a 6.6 nm channel length silicon FinFET. The discrete dopants have been distributed randomly in the source/drain region of the device. Due to the small dimensions of the FinFET, a quantum transport formalism based on the non-equilibrium Green's functions has been deployed. The transfer characteristics for several devices that differ in location and number of dopants have been calculated. Our results demonstrate that discrete dopants modify the effective channel length and the height of the source/drain barrier, consequently changing the channel control of the charge. This effect becomes more significant at high drain bias. As a consequence, there is a strong effect on the variability of the on-current, off-current, sub-threshold slope, and threshold voltage. Finally, we have also calculated the mean and standard deviation of these parameters to quantify their variability. The obtained results show that the variability at high drain bias is 1.75 larger than at low drain bias. However, the variability of the on-current, off-current, and sub-threshold slope remains independent of the drain bias. In addition, we have found that a large source to drain current by tunnelling current occurs at low gate bias.

Investigation on phonon scattering in a GaAs nanowire field effect transistor using the non-equilibrium Green's function formalism

Using quantum transport simulations, the impact of electron-phonon scattering on the transfer characteristic of a gate-all-around nanowire (GaAs) field effect transistor (NWFET) has been thoroughly investigated. The Non-Equilibrium Green's Function formalism in the effective mass approximation using a decoupled mode decomposition has been deployed. NWFETs of different dimensions have been considered, and scattering mechanisms including acoustic, optical and polar optical phonons have been included. The effective masses were extracted from tight binding simulations. High and low drain bias have been considered. We found substantial source to drain tunnelling current and significant impact of phonon scattering on the performance of the NWFET. At low drain bias, for a 2.2 × 2.2 nm2 cross-section transistor, scattering caused a 72%, 77%, and 81% decrease in the on-current for a 6 nm, 10 nm, and 20 nm channel length, respectively. This reduction in the current due to scattering is influenced by the increase in the tunnelling current. We include the percentage tunnelling for each valley at low and high drain bias. It was also found that the strong quantisation caused the relative position of the valleys to vary with the cross-section. This had a large effect on the overall tunnelling current. The phonon-limited mobility was also calculated, finding a mobility of 950 cm2/V s at an inversion charge density of 1012 cm−2 for a 4.2 × 4.2 nm2 cross-section device.

Parasitic bipolar effect in ultra-thin FD SOI MOSFETs

The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5–10nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond VD>1.0V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations.

Approximate analytical channel potential model of poly-Si thin film transistors operated in the strong inversion region under the high gate and low drain biases

An approximate analytical channel potential model of polycrystalline silicon thin film transistors operated in the strong inversion region under the high gate and low drain biases is proposed. Thus, the linear relationship between the channel potential and the drain voltage is derived in the strong inversion region under the above bias condition when the polysilicon layer is ultrathin. This model agrees with the two-dimensional-device simulation results under different gate voltages, different drain voltages and different channel lengths. By comparing the relative errors between the model and the simulation results, it presents that this model is more suitable under the higher gate voltage Vg or the lower drain voltage Vd, regardless of the channel length. And this approximate analytical model is helpful in solving the two- dimensional-device problem by one-dimensional Poisson's equation since the drain bias is taken into account in the channel potential.

3-D Finite Element Monte Carlo Simulations of Scaled Si SOI FinFET With Different Cross Sections

Nanoscaled Si SOI FinFETs with gate lengths of $12.8$ and $10.7$ nm are simulated using 3-D finite element Monte Carlo (MC) simulations with 2-D Schrodinger-based quantum corrections. These nonplanar transistors are studied for two cross sections: rectangular-like and triangular-like, and for two channel orientations: $\langle 100\rangle$ and $\langle 110\rangle$ . The $10.7$ -nm gate length rectangular-like FinFET is also simulated using the 3-D nonequilibrium Green’s functions (NEGF) technique and the results are compared with MC simulations. The $12.8$ and $10.7$ nm gate length rectangular-like FinFETs give larger drive currents per perimeter by about 33–37% than the triangular-like shaped but are outperformed by the triangular-like ones when normalised by channel area. The devices with a $\langle 100\rangle$ channel orientation deliver a larger drive current by about $11$ % more than their counterparts with a $\langle 110\rangle$ channel when scaled to $12.8$ nm and to $10.7$ nm gate lengths. $I_{D}-V_{G}$ characteristics obtained from the 3-D NEGF simulations show a remarkable agreement with the MC results at low drain bias. At a high drain bias, the NEGF overestimates the on-current from about $V_{G}-V_{T}=0.3$ V because the NEGF simulations do not include the scattering with interface roughness and ionized impurities.

Methodology for 1/f noise parameter extraction for high-voltage MOSFETs

This paper proposes a detailed low frequency noise (LFN) parameter extraction method for high-voltage (HV) MOSFETs at low (50mV) and medium (3V) drain biases. In Vd=3V region, noise coming from the channel is dominant while in linear region there is an extra contribution of noise from the drift region part especially for long-channel devices in strong inversion region. Flicker noise of 50V and 20V N- and P-channel HV-MOSFETs was measured over a large current range from weak to strong inversion, making possible the extraction of the noise parameters related to the different noise contributions, such as mobility fluctuations in low current regime, carrier number fluctuations and Coulomb scattering in medium and high current regime. In some cases, series resistance noise contribution especially at high current is apparent as well. The parameter extraction procedure is devised for a recently established charge-based flicker noise model for HV-MOSFETs. Noise parameters related to the carrier number fluctuation effect in the gate oxide extension in drift region are also extracted in high current regime of long-channel devices under low drain bias condition. The frequency exponent AF related to the slope of the measured noise spectra is also extracted. Measurements and analysis include both long as well as short N- and P-channel HV-MOSFETs.

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds=−0.1V and gate channel length L=1μm), and seems to be dominated by a minimally required critical length (L=0.2μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.

Quantum transport characteristics in single and multiple N-channel junctionless nanowire transistors at low temperatures

Single and multiple n-channel junctionless nanowire transistors (JNTs) are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures (10 K–100 K) and variable drain bias voltages (10 mV–90 mV). Transfer characteristics exhibit current oscillation peaks below flat-band voltage (VFB) at temperatures up to 75 K, which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional (1D) channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.

Modeling Carrier Mobility in Nano-MOSFETs in the Presence of Discrete Trapped Charges: Accuracy and Issues

This paper investigates the accuracy and issues of modeling carrier mobility in the channel of a nanoscaled MOSFET in the presence of discrete charges trapped at the channel/oxide interface. By comparing drift-diffusion (DD) and Monte Carlo (MC) simulation results, a quasi-local mobility model accounting for the complex scattering profile associated with a trapped carrier at the center of the channel is firstly derived. The accuracy of this model is evaluated on a test-bed 25-nm MOS transistor at low drain bias condition and for several applied gate biases. The issues in extending this mobility model to high drain biases regime and to the case of randomly positioned trapped charges are then discussed in the second part of this paper. Our findings show that DD simulations can maintain computational efficiency and accuracy at low drain biases, when a proper mobility model is used to describe the impact of discrete trapped charges. On the other hand, more complex corrections, that go beyond the simple mobility modification, are necessary to compensate the different carrier concentrations between DD and MC approaches at high drain biases.

Analysis of Carrier Transport in Short-Channel MOSFETs

A method for extracting transport parameters in short-channel FETs is presented in the context of the Lundstrom model for quasi-ballistic short-channel FETs. The parameters extracted from measured data are unidirectional thermal velocity, critical length, and mean free path at low and high drain biases. The method is based on an analysis of the channel length dependence of apparent mobility and virtual-source (VS) velocity, which are obtained by fitting the VS model to measured data. Data from (100)-oriented undoped-body extremely thin silicon-on-insulator FETs with neutral stress liners are used to validate the method. Since this method does not assume any theoretical knowledge of band structure parameters, it can be applied to short-channel FETs with any geometry, any channel material, and with unknown levels of channel stress.

Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET

A 3-D quantum-corrected drift-diffusion (DD) simulation study of three sources of statistical variability, including discrete random dopants (RDs), line-edge roughness (LER), and metal gate workfunction (MGW) was performed for a 14-nm gate length In0.53Ga0.47As FinFET in the subthreshold region using Fermi-Dirac statistics. This paper has been done at both low (0.05 V) and high drain biases (0.6 V). The LER variability is characterized by the root mean square amplitude (Δ) and correlation length (Λ), and the MGW variability by the metal grain size (GS). The RD-induced variation σ VT = 6 mV is similar to that observed in Si SoI FinFETs. The LER-induced threshold voltage variations (σ VT <; 6 mV) are similar to the RD variations when Δ = 1 nm, and smaller than the observed in Si SoI FinFETs (18 mV). For larger A, the LER exhibits σ VT ranging from 11 mV when Λ = 10 nm and Δ = 2 nm to 19 mV when Λ = 20 nm and Δ = 3 nm. The MGW variations are the dominant source of variability in the subthreshold characteristics, the σ VT ranges from 106 mV when GS = 10 nm to 43 mV when GS = 3 nm, which is larger than those observed in equivalent TiN metal-gate Si FinFETs.

Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits

In this paper, we comprehensively review the impacts of single-trap-induced random telegraph noise (RTN) on FinFET, Ge/Si Nanowire FET and Tunnel FET (TFET). The resulting influences on the thermionic-based current conduction such as FinFET, Si-NW FET and Ge-NW FET (at low drain bias) as well as interband tunneling dominated current conduction such as TFET and high-drain-biased Ge-NW FET are extensively addressed in device and circuit level. The location of the trap is shown to have profound impacts and the impacts vary with bias conditions and trap types. The worst-case analysis of the stability/performance and leakage/delay for all possible trapping/detrapping RTN combinations are investigated for FinFET, Si-/Ge-NW FETs and TFET based 6T/8T SRAM cells and logic circuits.

Current–Voltage Model of Bulk Fin Field-Effect Transistors with a Half-Circle Corner

The drain current of fully depleted (FD) nanoscale bulk FinFETs with the top-channel of a half-circle shape was modeled, for the first time, systematically in all operational regions and compared with the data obtained from three-dimensional (3D) device simulation. In the current model of these devices, it is very important to have accurate threshold voltages for side-channels and top-channel, and take the field penetration effect induced by the top-gate near the top of a fin body into account the threshold voltage (Vth) models for top-channels and side-channels, respectively. So, we obtained successfully the Vth models [Vth0t (Vth model of top-channel at a low drain bias) and Vth0s (Vth model of side-channels at a low drain bias)] considering the field penetration effect for both channels (top- and side-channels) to model the current behaviors in the doped bulk FinFETs with the top-channel of a half-circle shape. Our compact current model with Vth0t and Vth0s predicted accurately the current behaviors of the devices and shown a good agreement with 3D simulation.

Measurement and Compact Modeling of 1/f Noise in HV-MOSFETs

This paper investigates 1/f noise behavior under low and high drain biases of high-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) (HV-MOSFETs). A dedicated setup is presented which allows measuring low-frequency (LF) noise of lateral double-diffused MOSFETs (LDMOSFETs) up to 200 V at the drain. LF noise spectra of n- and p-channel LDMOSFETs were measured over a large range of gate and drain bias conditions and modeled using a recently established physics-based compact model of HV-MOSFETs. The investigated devices confirm that the overall noise is mostly dominated by the noise originating in the channel, while the drift-region-generated noise only is apparent in linear operation.

Study of individual phonon scattering mechanisms and the validity of Matthiessen's rule in a gate-all-around silicon nanowire transistor

In this paper, we investigate the impact of different phonon scattering mechanisms on the performance of a small silicon gate-all-around nanowire field effect transistor. The Non-equilibrium Green's function (NEGF) framework in the effective mass approximation is used to describe the carrier transport in a wide range of bias conditions. For all gate bias conditions, acoustic phonons are found to be the most important scattering mechanism. At low drain bias, the total impact of the phonons increases monotonically with the gate bias as all the contributions from different phonons increase, but at high drain bias the drain current reduction remains almost constant. At high gate bias conditions, the calculations show a different behaviour for acoustic phonons at low and high drain bias, which substantially influences the total impact of phonon scattering at high gate biases. The drain current reduction, including all phonons, is in agreement with previous simulations using a tight-binding/NEGF approach [M. Luisier and G. Klimeck, Phys. Rev. B 80, 155430 (2009)]. We find a violation of Matthiessen's rule of 13%. A value of 16% is obtained through the use of a Green-Kubo formula, which includes a self-consistent calculation of the retarded Green's function. However, an overestimation of 23% is found if a semi-classical Kubo expression is used.