Low Drain Bias Research Articles

Bipolar snapback in junctionless transistors for capacitorless dynamic random access memory

In this work, we analyze the snapback effect and extract the effective bipolar current gain in junctionless nanotransistors. The optimal electron and hole concentrations required to trigger and sustain bipolar snapback in junctionless transistors have been evaluated. The occurrence of snapback at lower drain bias (≅ 2 V) in junctionless devices in comparison to conventional inversion mode transistors demonstrates the enormous potential for static power reduction in capacitorless dynamic random access memories. High values (40–70) of effective bipolar current gain achieved in optimally designed junctionless transistors can be utilized to improve the sensing margin for dynamic memories.

Modeling of transient drain current overshoot in polycrystalline silicon thin-film transistors

Turn-on transient drain current in polycrystalline silicon thin-film transistors is investigated. We consider two mechanisms responsible for causing the overshoot current, i.e., the carrier trap effect (CTE) and the self-heating effect (SHE). Under low drain bias, current decay is described by the power-law relaxation indicating CTE. Meanwhile, when input power is increased, the overshoot component associated with SHE is superposed, for which the stretched exponential function provides a better representation. We discuss the mechanisms behind the observed characteristics, and propose a semi-empirical equivalent circuit model to reproduce the transient behavior especially focusing on CTE.

QUASI TWO-DIMENSIONAL ANALYSIS OF THE SURFACE POTENTIAL FOR POLY-Si THIN FILM TRANSISTORS BASED ON THE CHANNEL POTENTIAL

A quasi two-dimensional analysis of the surface potential for polycrystalline silicon thin film transistors based on the channel potential is developed. Since the drain bias is taken into account, the surface potential model is proposed to approach the surface potential in the two-dimensional device although this model is developed by solving the one-dimensional Poisson's equation. This model is derived under the relative high gate and low drain biases while devices are operated in the strong inversion region. It is obtained by introducing the channel potential expression containing the drain bias and the normalized channel distance. And this channel-potential-based surface potential model is verified by the two-dimensional-device simulator in various gate voltages, various drain voltages and various channel lengths. This model well characterizes the surface potential distribution along the device's channel in the strong inversion region under the relative high gate and low drain biases.

Planar InAs/AlSb HEMTs With Ion-Implanted Isolation

The fabrication and performance of planar InAs/AlSb high-electron-mobility transistors (HEMTs) based on ion-implantation isolation technology are reported. Ar atoms have been implanted at an energy of 100 keV and with a dose of 2 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> in order to induce device isolation. The InAs/AlSb HEMT exhibited a maximum drain current of 900 mA/mm, a peak transconductance of 1180 mS/mm, and an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ratio of 210 GHz/180 GHz at a low drain bias of 0.3 V. The combination of excellent stability against oxidation with the high device isolation demonstrated by the implantation technique can dramatically improve the suitability of InAs/AlSb HEMTs for high-frequency and ultralow-power MMIC applications.

Non-equilibrium Green’s function analysis of cross section and channel length dependence of phonon scattering and its impact on the performance of Si nanowire field effect transistors

In this paper, we study the effect of phonon scattering in silicon nanowire field effect transistors (NWFET) using a Non-equilibrium Green’s function formalism in the effective mass approximation. The effect of electron-phonon scattering on the current voltage characteristics at high and low drain bias is investigated in detail. A wide range of cross-sections (from 2.2 × 2.2 to 6.2 × 6.2 nm2) and channel lengths (from 6 to 40 nm) are considered. The impact of phonon scattering on the electron current in different regions of the device characteristics is studied. Simulations including scattering in the whole transistor are compared with corresponding simulations in which scattering is only in the channel. Phonon limited mobility dependence on the NWFET cross-section and channel length is studied. The ballisticity coefficient, as a function of the channel length and gate voltage, is also computed for various channel cross-sections and lengths at high drain bias. The paper demonstrates that tunneling plays an important role in understanding the effect of phonon scattering at short channel lengths.

SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms

Several concepts of capacitor-less single-transistor (1T) DRAM have recently been proposed to overcome the scaling limitations of bulk DRAMs. In this study, we focus on the comparison of two programming mechanisms of 1T-DRAMs: the impact ionization (II), the most common mechanism to store charges in the body of the cell, and the meta-stable dip (MSD) effect. The impact of the gate length and channel thickness reduction on both the II and the MSD programming mechanisms has been investigated using dynamic measurements on conventional Fully Depleted SOI (FDSOI) transistors. In the absence of any customization of technology and device architecture, it is found that MSD programming is superior and demonstrates higher resilience to the MOSFET scaling. These promising performances arise from the dynamic coupling between the front and back gates and from the use of low drain bias.

Field-dependent carrier trapping induced kink effect in AlGaN/GaN high electron mobility transistors

An anomalous kink effect featuring an abrupt recovery of drain current following current collapse is observed in the room-temperature output characteristics of AlGaN/GaN high electron mobility transistors. The kink is largely caused by trapping electrons from the gate leakage current by deep levels within the AlGaN barrier at high drain bias, resulting in a positive shift in threshold voltage and a reduction in reverse gate leakage current. The release of the trapped electrons is likely due to impact ionization of traps by hot electrons, which starts to play a role at relatively lower drain bias. Both sub-bandgap illumination and temperature rise could reduce the kink.

Gate-induced drain leakage in FD-SOI devices: What the TFET teaches us about the MOSFET

This paper compares the gate-induced drain leakage (GIDL) in fully-depleted (FD) silicon-on-insulator (SOI) tunneling field effect transistor (TFET) and in standard metal-oxide-semiconductor FET (MOSFET) fabricated in the same process. The measurements show that the MOSFET GIDL current is lower than the GIDL in a TFET with the same junction doping, especially for devices with thick gate oxide and under low drain bias. A model describing lateral band-to-band tunneling (BTBT) is developed for GIDL in the FD-SOI TFET. By combining the model of gate-controllable tunneling diode in series with a field effect diode, we achieve an accurate picture of GIDL in FD-SOI MOSFETs.

Simulation of “Ab Initio” Quantum Confinement Scattering in UTB MOSFETs Using Three-Dimensional Ensemble Monte Carlo

In this paper, we report a 3-D Monte Carlo (MC) simulation methodology that includes complex quantum confinement effects captured through the introduction of robust and efficient density gradient (DG) quantum corrections (QCs), which has been used to introduce “ab initio ” scattering from quantum confinement fluctuations in ultrathin body silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs) through the real space trajectories of the particles driven by the DG effective quantum potential and to study the enhanced current variability due to the corresponding transport variations. A “frozen field” approximation, where neither the field nor the QCs are updated, has been used to examine the dependence of mobility on silicon thickness in large self-averaging devices. This approximation, along with the MC simulations that are self-consistent with Poisson's equation, is applied to study the variability of on-current due to random body thickness fluctuations in thin-body MOSFETs at low and high drain biases.

Electrical performance study of 25 nm Ω-FinFET under the influence of gamma radiation: A 3D simulation

In this research paper, a 3D process simulation of 25nm n-channel Ω-FinFET and the effect of Gamma radiation on device characteristics have been studied. Device simulations are carried out under the influence of Gamma radiation under varying does conditions from 100Krad (SiO2) to 10Mrad (SiO2). Effects of Gamma radiation on the threshold voltage, transfer characteristics, drive current, off-state leakage current and subthreshold characteristics have been studied. Extracted parameters for virgin and irradiated devices have been compared in order to understand the degradation in the electrical characteristics of the Ω-FinFET under study. Simulation results under the low drain and high drain bias has been reported and discussed. It is found that Ω-FinFET delivers better performance under irradiation as compared with conventional single gate MOS structures. Ω-FinFET is shown to be significantly tolerant to gamma radiation upto dose of 5Mrad (SiO2). In addition, the influence of quantum effects on this nanoscale device is investigated in detail. Sentaurus simulation results obtained has been compared with the reported experimental data.

Variable temperature characterization of low-dimensional effects in tri-gate SOI MOSFETs

We report on variable temperature charge transport measurements of tri-gate silicon-on-insulator MOSFETs with fin widths of 11 nm, fin heights of 58 nm and gate lengths ranging from 80 nm to 250 nm. Reproducible inflection points were observed in drain current vs. gate voltage data acquired at low temperature (4–8 K) and low drain bias (0.1 mV), yielding oscillations in the extracted transconductance data which are consistent with formation of a one-dimensional electron gas in the channel. Simulations of the variation in fin potential with gate voltage indicate transport through ∼3 sub-bands per fin at gate overdrive of 100 mV above threshold. Observed multi-peak envelopes in measured transconductance vs. gate voltage data for multiple-fin devices suggest sub-band separations ∼20 mV, in reasonable agreement with simulation results (27–55 mV). The measured conductance per fin at low temperatures (4–6 K) was on the order of the quantum conductance, consistent with diffusive transport through multiple sub-bands. Measured transconductance features were largely reproducible for repeated measurements on a given device, although slight variations could be observed, possibly due to quantum interference or interface charges.

Organic transistor model with nonlinear injection: Effects of uneven source contact on apparent mobility and threshold voltage

This work addresses nonlinear characteristics observed in organic field effect transistors due to uneven injection at the source contact. A self-consistent OFET model has been developed for bottom-contact organic transistor, and is described in detail. Most relevant contact parasitics are taken into account, such as source and drain series resistances, leakage source/drain resistance, and of course nonlinear charge injection at the source contact, being the focus of this work. The drain current calculation is fully self-consistent and implemented in an original manner. First, results are compared with literature and internal data on poly(3-hexylthiophene) bottom contact transistors presenting nonlinear behavior. In both cases, a single constant parameter set is used to fit all the transistor characteristic with good agreement. All extracted parameters, such as mobility or internal source contact voltage drop, are coherent with the device physics, showing the model capability to be used as a characterization tool. Following, it is shown that, in presence of series resistances and nonlinear injection, the usual mobility extraction procedure may become highly unreliable, showing a pronounced apparent mobility dependence with gate bias. Also the effective threshold voltage is shown to shift towards higher values due to the potential drop at the source contact. This is quantitatively described. Finally, the link between nonlinear injection and instabilities and breakdown conditions is established. It is shown that for a source/channel barrier height greater than 0.5–0.6 eV, the 5–6 MV cm −1 breakdown limit is reached even at very low drain bias.

Temperature-Dependent $I$– $V$ Characteristics of a Vertical $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Tunnel FET

We report on the experimental temperature-dependent characteristics of vertical In0.53Ga0.47As tunnel field-effect transistors (TFETs) at low drain bias to provide key insight into its device operation and design. Leakage floor (IOFF) is determined by the ungated p+-i-n+ reverse bias leakage and is dominated by Shockley-Read-Hall generation-recombination current. The temperature dependence of subthreshold slope arises from tunneling into mid-gap states at the oxide-semiconductor interface, followed by thermal emission into the conduction band. At intermediate gate voltages, pure band-to-band tunneling dominates, while at higher gate voltages, current transport is diffusion limited. The temperature-dependent study of In0.53Ga0.47As TFET highlights the importance of passivating the III-V and dielectric interface.

Improvement on the noise performance of InAs-based HEMTs with gate sinking technology

Improvement on the RF and noise performance for 80 nm InAs/In 0.7Ga 0.3As high-electron mobility transistor (HEMT) through gate sinking technology is presented. After gate sinking at 250 °C for 3 min, the device exhibited a high transconductance of 1900 mS/mm at a drain bias of 0.5 V with 1066 mA/mm drain–source saturation current. A current-gain cutoff frequency ( f T ) of 113 GHz and a maximum oscillation frequency ( f max) of 110 GHz were achieved at extremely low drain bias of 0.1 V. The 0.08 × 40 μm 2 device with gate sinking demonstrated 0.82 dB minimum noise figure and 14 dB associated gain at 17 GHz with only 1.14 mW DC power consumption. Significant improvement in RF and noise performance was mainly attributed to the reduction of gate-to-channel distance together with the parasitic source resistance through gate sinking technology.

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.

Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage

A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved.

Formation of sub-micrometer polycrystalline-SiGe thin-film transistors by using a thinned channel layer

A sub-micron poly-SiGe TFT device, operating at a drain bias of 1.5 V, is proposed by using a thinned channel layer. A thinner channel layer may lead to better good gate control over the entire channel region. Hence, a thinner channel layer may lead to better on-state conduction at low operation voltage, but sustain larger vertical electric field under negative gate bias. A thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-SiGe TFT device with a thinner channel layer, in spite of the more enhanced vertical electric field, the leakage current would be more effectively suppressed primarily due to the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-SiGe TFT device with 20-nm channel layer can cause an off-state leakage of about 10 pA/μm at a drain bias of 1.5 V, and an on/off current ratio of about seven orders can be achieved.

On Backscattering and Mobility in Nanoscale Silicon MOSFETs

The DC current-voltage characteristics of an n-channel silicon MOSFET with an effective gate length of about 60 nm are analyzed and interpreted in terms of scattering theory. The experimental results are found to be consistent with the predictions of scattering theory - the drain current is closer to the ballistic limit under high drain bias than under low drain bias, and the on-current in strong inversion is limited by a small portion of the channel near the source. The question of how the low- and high- V DS drain currents are related to the near-equilibrium, long-channel mobility is also addressed. In the process of this analysis, theoretical and experimental uncertainties that make it difficult to extract numerically precise values of the scattering parameters are identified.

Investigation of Low-Frequency Noise in N-Channel FinFETs From Weak to Strong Inversion

This paper presents the low-frequency noise (LFN) characteristics of symmetric double-gate n-FinFETs from weak to strong inversion at low drain bias. The noise-generation mechanism is investigated. The measured drain-current noise spectral density shows that LFN in the weak-inversion subthreshold region can be well described by the mobility-fluctuation model due to volume-inversion conduction behavior, which is very different from those normally observed in the bulk NMOS. The analytical expression for the drain-current noise spectral density is derived, with the Hooge parameter alpha <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> being extracted. In the strong-inversion linear region, the gate-voltage dependence of the room-temperature noise data agrees with the number-fluctuation model, but the slope of the frequency dependence is less than one. To determine the causes of the observed deviation from the unity slope, detailed measurements of the temperature dependence of the noise power spectra are performed, and results from two devices are presented in this paper. It is found that both the magnitude and the frequency dependence of the drain-voltage noise spectral density vary greatly in the range between 223 K and 383 K. The experimental results are compared with two models derived based on the Dutta-Horn and the McWhorter models. It is shown that the thermal-activation model of Dutta-Horn is more convincing than the latter, which shows that the noise is due to the capture and emission of carriers by oxide traps through thermal activation. The surface trap density at specific activation energy is extracted.

Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current

We report the first study of the effect of strain on tunneling field-effect transistor (TFET) characteristics. Double-gate silicon TFETs were employed. It was found that tensile strain increases the drain current, whereas compressive strain reduces the drain current. This is attributed to strain-induced band splitting and carrier repopulation and provides guidelines on strain engineering of TFETs. An elaborate study of the dependence of the electrical characteristics of TFET on temperature is also reported. It was observed that on-state tunneling current exhibits a positive temperature dependence at low drain bias condition ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 1 V), whereas opposite behavior was observed when <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 1.5 V. When the device temperature is increased, enhancement of the drain current at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 1 V results from band gap narrowing, whereas reduction in the drain current at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 1.5 V is attributed to the decrease in the electric field at the tunneling junction.