Formation of sub-micrometer polycrystalline-SiGe thin-film transistors by using a thinned channel layer

Abstract

A sub-micron poly-SiGe TFT device, operating at a drain bias of 1.5 V, is proposed by using a thinned channel layer. A thinner channel layer may lead to better good gate control over the entire channel region. Hence, a thinner channel layer may lead to better on-state conduction at low operation voltage, but sustain larger vertical electric field under negative gate bias. A thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-SiGe TFT device with a thinner channel layer, in spite of the more enhanced vertical electric field, the leakage current would be more effectively suppressed primarily due to the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-SiGe TFT device with 20-nm channel layer can cause an off-state leakage of about 10 pA/μm at a drain bias of 1.5 V, and an on/off current ratio of about seven orders can be achieved.