On short channel effects in high voltage JFETs: A theoretical analysis

Abstract

In this work, the impact of Short Channel Effects (SCEs), particularly Drain Induced Barrier Lowering (DIBL) on the performance of a high voltage Silicon Carbide (SiC) JFET has been thoroughly investigated. Drift-Diffusion simulations of on-state current-voltage characteristics and breakdown performance have been completed for different gate junction depths (xj) and mesa widths (MW). Due to the short channel length, realistic implant doping profiles extracted from experimentally calibrated Monte-Carlo based SRIM simulations have been used. Two suitable designs to eliminate premature DIBL-induced failure have been found: xj = 0.7 µm for MW=1.75 µm, and xj = 1 µm for MW=2 µm. We found that a 0.3 µm junction depth has a breakdown voltage of only 50 V due to collapse of the source-drain barrier at a relatively low drain bias. Threshold voltage (Vth) decreases with increasing junction depth, approaching 0 V. This is due to a combination of greater lateral straggling of implanted ions and improved electrostatic control of the channel. Our calculations demonstrate that the most robust option to mitigate DIBL and consequently early breakdown is to maintain xj≥1 µm. At this depth, the threshold voltage has a weak dependence on drain bias, indicating diminishing SCEs. Decreasing the mesa width mitigates early breakdown but requires a mesa width of less than 1.75 µm, which poses fabrication challenges.