Logic Family Research Articles

Binary Counters Using Adiabatic Quantum-Flux-Parametron Logic

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this article, we design binary counters, namely an up counter, a down counter, and an up/down counter, based on AQFP logic. These binary counters are T-flip-flop-based and count logic 1s in the input signal that is synchronized with excitation currents, which clock the counters. The internal state of a T flip-flop changes when the internal state of the previous T flip-flop changes from logic 1 to 0 and from logic 0 to 1 for the count-up and count-down operations, respectively. Each internal state of a T flip-flop is read out serially by a buffer chain coupled to the T flip-flops. We fabricate 4-bit up, down, and up/down counters using the AIST 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb high-speed standard process and demonstrate their correct operation at low frequency. This is the first demonstration of binary counters based on AQFP logic.

Non-volatile reconfigurable spin logic device: parallel operations

A new proposal is given for designing a non-volatile, completely spin logic device, that can be reprogrammed for different functional classical logical operations. We use the concept of bias driven spin dependent circular current and current induced magnetic field in a quantum ring under asymmetric ring-to-electrode interface configuration to implement all the Boolean operations. We extend our idea to build two kinds of parallel computing architectures for getting parallelized operations, all at a particular time. For one case, different kinds of parallel operations are performed in a single device, whereas in the other type all the possible inputs of a logic gate are processed in parallel and all the outputs are read simultaneously. The performance and reliability are investigated in terms of power, delay and power-delay-product and finally the system temperature. We find that both the individual and simultaneous logic operations studied here are much superior compared to the operations performed in different conventional logic families like complementary metal oxide semiconductor logic, transistor-transistor logic, etc. The key advantage is that we can perform several logic operations, as many as we wish, repeating the same or different logic gates using a single setup, which indeed reduces wiring in the circuits and hence consumes much less power. Our analysis can be utilized to design optimized logic circuits an nano-scale level.

Energy Efficient Adiabatic Logic Circuit for Improve Security in DPA Resistant RFID

A Differential Power Analysis (DPA) attack is an exploit which overcomes the hardware and software security by analyzing the correlation between electricity usage of a chip in a device and the encryption key. These attacks are non-invasive, leading an intruder to crack a system without leaving any trace. CMOS Technology is prone to DPA attack because of higher power dissipation. A DPA resistant adiabatic technique has been analyzed which has lower power dissipation when compared to the CMOS technology. The conventional Positive Feedback Adiabatic Logic (PFAL) suffers from certain non-adiabatic energy loss. Hence, Energy Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) is proposed which reduces the non-uniform power consumption, preventing information leakage thus securing the system from DPA attacks. Thus the proposed EE-SPFAL is used to design logical circuits such as buffer, OR-XNOR and AND-NAND gate. It is proved that the information leakage in the form of current consumption takes place in PFAL buffer whereas current consumption traces in EE-SPFAL circuits are uniform, depicting the ability of the proposed logic family to resist DPA attack. The simulation was done using Cadence virtuoso 180 nm technologies.

Hybrid Pass Transistor Logic With Ambipolar Transistors

In comparison to the conventional complementary pull-up and pull-down logic structure, the pass transistor logic (PTL) family reduces the number of transistors required to perform logic functions, thereby reducing both area and power consumption. However, this logic family requires inter-stage inverters to ensure signal integrity in cascaded logic circuits, and inverters must be used to provide each logical input signal in its complementary form. These inverters and complementary signals increase the device count and significantly degrade overall system efficiency. Dual-gate ambipolar field-effect transistors natively provide a single-transistor XNOR operation and permit highly-efficient and compact circuits due to their ambipolar capabilities. Similar to PTL, logic circuits based on ambipolar field-effect transistors require complementary signals. Therefore, numerous inverters are required, with significant energy and area costs. Ambipolar field-effect transistors are a natural match for PTL, as hybrid ambipolar-PTL circuits can simultaneously use these inverters to satisfy their necessity in both PTL and ambipolar circuits. We therefore propose a new hybrid ambipolar-PTL logic family that exploits the compact logic of PTL and the ambipolar capabilities of ambipolar field-effect transistors. Novel hybrid ambipolar-PTL circuits were designed and simulated in SPICE, demonstrating strong signal integrity along with the efficiency advantages of using the required inverters to simultaneously satisfy the requirements of PTL and ambipolar circuits. In comparison to the ambipolar field-effect transistors in the conventional CMOS logic structure, our hybrid full adder circuit can reduce propagation delay by 47%, energy consumption by 88%, energy-delay product by a factor of 9, and area-energy-delay product by a factor of 20.

INQUISITIVE BISIMULATION

AbstractInquisitive modal logic, InqML, is a generalisation of standard Kripke-style modal logic. In its epistemic incarnation, it extends standard epistemic logic to capture not just the information that agents have, but also the questions that they are interested in. Technically, InqML fits within the family of logics based on team semantics. From a model-theoretic perspective, it takes us a step in the direction of monadic second-order logic, as inquisitive modal operators involve quantification over sets of worlds. We introduce and investigate the natural notion of bisimulation equivalence in the setting of InqML. We compare the expressiveness of InqML and first-order logic in the context of relational structures with two sorts, one for worlds and one for information states, and characterise inquisitive modal logic as the bisimulation invariant fragment of first-order logic over various natural classes of two-sorted structures.

THE MODAL LOGICS OF KRIPKE–FEFERMAN TRUTH

AbstractWe determine the modal logic of fixed-point models of truth and their axiomatizations by Solomon Feferman via Solovay-style completeness results. Given a fixed-point model $\mathcal {M}$ , or an axiomatization S thereof, we find a modal logic M such that a modal sentence $\varphi $ is a theorem of M if and only if the sentence $\varphi ^*$ obtained by translating the modal operator with the truth predicate is true in $\mathcal {M}$ or a theorem of S under all such translations. To this end, we introduce a novel version of possible worlds semantics featuring both classical and nonclassical worlds and establish the completeness of a family of noncongruent modal logics whose internal logic is nonclassical with respect to this semantics.

Adiabatic Differential Cascode Voltage Switch Logic (A-DCVSL) for low power applications

In this paper, a new adiabatic logic family named as adiabatic differential cascode voltage-switch logic (A-DCVSL) for low power applications is presented. The family operates on a two-phase split level sinusoidal power clock instead of four-phase trapezoidal power clock. The proposed A-DCVSL circuits reduce the power dissipation by charge recovery and minimizing the peak current flow. The behavior of the inverter is analysed and the power dissipation of A-DCVSL circuit is mathematically modeled. The performance of A-DCVSL inverters is compared with other existing differential adiabatic logic families. A full subtractor is also designed to exhibit the benefits at the application level. The results confirm that the proposed A-DCVSL circuit outperforms in terms of power dissipation and can be adapted to the design of lower power applications. The simulations were performed on Tanner EDA tool using 32 nm PTM technology parameters.

A Data-Driven Asynchronous Neural Network Accelerator

Deep neural networks (DNNs) are revolutionizing machine learning, with unprecedented accuracy on many AI tasks. Energy-efficient neural acceleration is crucial in broadening DNN applications in cloud and mobile end devices. However, power-hungry clock networks limit the energy-efficiency of DNN accelerators. In this work, we propose a novel DNN hardware accelerator, called the asynchronous neural network processor (AsNNP). At the heart of AsNNP is a scalable hierarchy matrix multiply unit, with bit-serial processing elements working in parallel. It replaces the global clock networks with asynchronous handshake protocols to realize the synchronization and communication between each part, minimizing the dynamic power. Meanwhile, a fine-grain asynchronous pipeline based on weak-conditioned half-buffer (WCHB) is introduced to pipe successive computations in a data-driven manner, i.e., once data arrives computation begins, maximizing the throughput. These techniques enable AsNNP to work in a fully data-driven asynchronous communication fashion with optimized energy-efficiency. The proposed accelerator is implemented with quasi-delay-insensitive (QDI) clockless logic family and evaluated in a 65 nm process. Compared with the synchronous baseline, simulation results show that AsNNP offers 2.2× higher equivalent frequency and 1.59× lower power. Compared with state-of-the-art DNN accelerators, AsNNP shows 1.17×-4.97× energy-efficiency improvement.

Sequent-Type Calculi for Systems of Nonmonotonic Paraconsistent Logics

Paraconsistent logics constitute an important class of formalisms dealing with non-trivial reasoning from inconsistent premisses. In this paper, we introduce uniform axiomatisations for a family of nonmonotonic paraconsistent logics based on minimal inconsistency in terms of sequent-type proof systems. The latter are prominent and widely-used forms of calculi well-suited for analysing proof search. In particular, we provide sequent-type calculi for Priest's three-valued minimally inconsistent logic of paradox, and for four-valued paraconsistent inference relations due to Arieli and Avron. Our calculi follow the sequent method first introduced in the context of nonmonotonic reasoning by Bonatti and Olivetti, whose distinguishing feature is the use of a so-called rejection calculus for axiomatising invalid formulas. In fact, we present a general method to obtain sequent systems for any many-valued logic based on minimal inconsistency, yielding the calculi for the logics of Priest and of Arieli and Avron as special instances.

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

Design and Characterization of Track Routing Architecture for RSFQ and AQFP Circuits in a Multilayer Process

Place and route tools for synthesized superconductor logic circuits, either for dc-biased rapid single flux quantum (RSFQ) or ac-biased adiabatic quantum flux parametron (AQFP), are required to automate the design of complex logic circuits. For hand-crafted circuit layout, logic cells, clock, and bias distribution, and signal interconnect can be optimized for tight fit and the adherence to design rules. For complex systems with thousands of logic gates, a hand-crafted approach is not efficient and automated place and route tools are a necessity. Such tools require logic cell layout for placement with a minimum set of rules, followed by an interconnect design that allows maximum routability and strict adherence to layer fill requirements. In this article, we present the design and characterization of a routing architecture that allows rule-based automated place and route for both RSFQ and AQFP logic families. We show that a layout tile size of 10 × 10 μm can be designed to accommodate all design rules for layout fill densities, passive transmission line routing, bias current distribution, and the vias needed to stitch multiple ground planes and provide shielded signal and bias tracks. We also characterize the performance of the layout architecture in terms of transmission line parameters and bias current coupling with powerful simulation tools developed for the SuperTools project. The result is a track layout that doubles as chip fill, is now used for integrated circuit layout under SuperTools and is also applicable to any similar fabrication process with at least eight superconductor metal layers.

Soft Error Impact on FinFET and CMOS XOR Logic Gates

With the advance of computer systems, XORgates design became essential on arithmetic circuits.Atnanometer nodes, despite the electrical characterization, de-signers must to consider soft error impact on the circuits. Thechallenges change significantly as feature size are smaller, evenfor FinFET devices. The effects of Single Event Transientare dependent of the circuit topology. Thus, in this work, weevaluate the influence of nine XOR topologies on the radia-tion robustness, discussing the influence of logic family, the de-vice technology and environment factors as temperature, onthe radiation robustness. Also, this work explore the nominaland near-threshold operation of these XOR topologies. Resultsshows that FinFET devices are significantly more robust to theradiation effects. Also, most of PTL logic XORs topologiespresent about 40% of increase on the LET threshold. The de-pendence of temperature aggressively impact the FinFET tech-nology devices operating at near-threshold. Finally, the com-plete set of information provided in this work support design-ers to choose the most appropriate XOR topology accordingthe specific design requirements.

A More Unified Approach to Free Logics

Free logics is a family of first-order logics which came about as a result of examining the existence assumptions of classical logic. What those assumptions are varies, but the central ones are that (i) the domain of interpretation is not empty, (ii) every name denotes exactly one object in the domain and (iii) the quantifiers have existential import. Free logics usually reject the claim that names need to denote in (ii), and of the systems considered in this paper, the positive free logic concedes that some atomic formulas containing non-denoting names (namely self-identity) are true, while negative free logic rejects even the latter claim. Inclusive logics, which reject (i), are likewise considered. These logics have complex and varied axiomatizations and semantics, and the goal of this paper is to present an orderly examination of the various systems and their mutual relations. This is done by first offering a formalization, using sequent calculi which possess all the desired structural properties of a good proof system, including admissibility of contraction and cut, while streamlining free logics in a way no other approach has. We then present a simple and unified system of abstract semantics, which allows for a straightforward demonstration of the meta-theoretical properties, and offers insights into the relationship between different logics (free and classical). The final part of this paper is dedicated to extending the system with modalities by using a labeled sequent calculus, and here we are again able to map out the different approaches and their mutual relations using the same framework.

All-optical logic gates using dielectric-loaded waveguides with quasi-rhombus metasurfaces

Nanostructure and nanoantenna-based all-optical (AO) devices have attracted significant research interests in recent years due to their small size, high information capacity, ultrafast processing, low power consumption, and overall practicality. Here, in this Letter, we propose a novel metasurface having quasi-rhombus-shaped antennas to modulate optical modes in a dielectric-loaded waveguide for the realization of a complete family of logic gates including NOT, AND, OR, XOR, NAND, NOR, and XNOR. These logic operations are realized using destructive and constructive interferences between the input optical signals. The high contrast ratios of about 33.39, 27.69, and 33.11 dB are achieved for the NAND, NOR, and XNOR logic gates, respectively, with the speed as high as 108 Gb/s.

Dual-mode power reduction technique for real-time image and video processing board

In real-time image and video processing boards, power, speed, and area are the most often used measures for determining the performance of motion imagery applications. Due to technological advancement, power consumption has gained major attention in real-time image processing ability compared to speed. The increase in on-chip temperature due to larger power consumption has resulted in reduced operating life of chip and battery-driven devices. In this work, a new logic family has been introduced i.e., dual-mode logic (DML), which provides flexibility between the optimization of energy and delay (E-D optimization). This gate can be switched between two modes of operation that is a static mode (CMOS-like mode), which provides low power consumption and dynamic mode, which provides high speed. Recently, power leakage has become a dominant problem due to continuous data transfer among a large number of connected devices. Thus, to reduce power leakage, a self-controllable voltage level (SVL) power reduction technique is used along with DML logic. In the SVL technique, a maximum dc voltage is provided to the active load circuit on-demand or decrease the dc supplied to the load circuit in the standby mode. Integrating DML with the SVL technique reduces power consumption as well as leakage power. A 4-bit RCA, 8-bit RCA, and 16-bit RCA are used for verifying the proposed method and comparison of performance parameters is done with a conventional circuit. Complete circuit implementation and simulation are carried out in TANNER EDA version 13 tools with operating voltage of 1 V. The proposed system is further applied to real-time image, and we obtain the finest resolution level with minimum power consumption.

Progress towards innovative and energy efficient logic circuits

The integration of superconductive nanowire logic memories and energy efficient computing Josephson logic is explored. Nanowire memories are based on the integration of switchable superconducting nanowires with a suitable magnetic material. These memories exploit the electro-thermal operation of the nanowires to efficiently store and read a magnetic state. In order to achieve proper memory operation a careful design of the nanowire assembly is necessary, as well as a proper choice of the magnetic material to be employed. At present several new superconducting logic families have been proposed, all tending to minimize the effect of losses in the digital Josephson circuits replacing resistors by adequate combinations of inductors in the logic gates. Among those, the nSQUID concept relies on the propagation of vortices along underdamped Josephson transmission lines. While, in principle, this logic family provides very low dissipation, several issues, such as speed and stability, have yet to be addressed. The current status of design and testing of n-SQUID logic gates and circuits as well as of the design and implementation of the nanowire memories is reported

The synthesis method of logic circuits based on the iMemComp gates

The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of the row-oriented logic circuits based on the multi-input single-cycle iMemComp gates. The synthesis results show that the circuits generated from the proposed method outperform most of those RRAM based counterparts generated from the previous methods. Furthermore, the synthesis method of the array-oriented iMemComp logic circuits is proposed. The proposed array-oriented method generates the relatively high-performance logic circuits since both the row-based and the column-based single-cycle iMemComp gates are applied, and the generated circuits are relatively area-efficient because the intra-row and inter-row redundancies are utilized in the circuit mapping.

Binary Addition in Resistance Switching Memory Array by Sensing Majority.

The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory and operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T–1R array, which is faster than , , and other similar logic primitives.

Scalable readout interface for superconducting nanowire single-photon detectors using AQFP and RSFQ logic families.

We propose a scalable readout interface for superconducting nanowire single-photon detector (SSPD) arrays, which we call the AQFP/RSFQ interface. This interface is composed of adiabatic quantum-flux-parametron (AQFP) and rapid single-flux-quantum (RSFQ) logic families. The AQFP part reads out the spatial information of an SSPD array via a single cable, and the RSFQ part reads out the temporal information via a single cable. The hybrid interface has high temporal resolution owing to low timing jitter in the operation of the RSFQ part. In addition, the hybrid interface achieves high circuit scalability because of low supply current in the operation of the AQFP part. Therefore, the hybrid interface is suitable for handling many-pixel SSPD arrays. We demonstrate a four-pixel SSPD array using the hybrid interface as proof of concept. The measurement results show that the hybrid interface can read out all of the pixels with a low error rate and low timing jitter.

Logic Obfuscation Through Enhanced Threshold Voltage Defined Logic Family

Reverse engineering reveals the physical structure as well as the functionality of an intellectual property (IP) and integrated circuit (IC). This opens the door for IP/IC piracy, counterfeiting, and malicious attacks such as Trojan insertions. Camouflaged logic gates that have the same schematic architecture with identical layout is used to operate for different types of Boolean functions to prevent the de-layering of the chip. An enhanced threshold voltage (E-TVD) defined logic family is proposed in this brief that prevents the internal functionality from being revealed. Compared to previous TVD logic family, the total number of transistors and the cascaded transistors from supply to ground is reduced to enhance the overall performance. A 65nm process is used to compare the conventional TVD logic family and the proposed E-TVD logic family. Post layout simulation results show that the proposed E-TVD logic family for a 3-input logic gate is 34% area efficient, 45% faster, and consumes 40% less power compared to conventional TVD design.