Abstract
The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory and operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T–1R array, which is faster than , , and other similar logic primitives.
Highlights
Contemporary computing systems exhibit a deep memory hierarchy
The proposed logic family computes majority by sensing the data stored in a 1Transistor-1 Resistor (1T–1R) array, i.e., the inputs of the majority gate are the resistances of the memristors and the output is sensed as a voltage
A majority gate can be implemented in a 1T–1R array without necessitating any change in the sensing circuitry
Summary
Contemporary computing systems exhibit a deep memory hierarchy. The reason for such a hierarchy is that the non-volatile memory technology (FLASH) used as storage memory has an access time of hundreds of microseconds, while processors clocked at GHz need to access data in nanoseconds (Figure 1). Later researchers used the term near-memory computing or near data processing to refer to the same effort and they exploited 3D stacking of DRAM dies over logic die to compute near memory. Most researchers try to make their logic gates executable in an array configuration so that they can be exploited for in-memory computing. A Majority+NOT based memristive logic family is proposed Many such logic families using basic Boolean gates (OR, NOR, AND, NAND, XOR) have been proposed in recent years. The proposed logic family computes majority by sensing the data stored in a 1T–1R array, i.e., the inputs of the majority gate are the resistances of the memristors and the output is sensed as a voltage. A 1-bit full-adder is implemented in a 1T–1R array using the proposed method (Section 3.2) followed by comparison with other in-memory adders (Section 3.3) and conclusion (Section 4)
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