Adiabatic Differential Cascode Voltage Switch Logic (A-DCVSL) for low power applications

Abstract

In this paper, a new adiabatic logic family named as adiabatic differential cascode voltage-switch logic (A-DCVSL) for low power applications is presented. The family operates on a two-phase split level sinusoidal power clock instead of four-phase trapezoidal power clock. The proposed A-DCVSL circuits reduce the power dissipation by charge recovery and minimizing the peak current flow. The behavior of the inverter is analysed and the power dissipation of A-DCVSL circuit is mathematically modeled. The performance of A-DCVSL inverters is compared with other existing differential adiabatic logic families. A full subtractor is also designed to exhibit the benefits at the application level. The results confirm that the proposed A-DCVSL circuit outperforms in terms of power dissipation and can be adapted to the design of lower power applications. The simulations were performed on Tanner EDA tool using 32 nm PTM technology parameters.