Design and Characterization of Track Routing Architecture for RSFQ and AQFP Circuits in a Multilayer Process

Abstract

Place and route tools for synthesized superconductor logic circuits, either for dc-biased rapid single flux quantum (RSFQ) or ac-biased adiabatic quantum flux parametron (AQFP), are required to automate the design of complex logic circuits. For hand-crafted circuit layout, logic cells, clock, and bias distribution, and signal interconnect can be optimized for tight fit and the adherence to design rules. For complex systems with thousands of logic gates, a hand-crafted approach is not efficient and automated place and route tools are a necessity. Such tools require logic cell layout for placement with a minimum set of rules, followed by an interconnect design that allows maximum routability and strict adherence to layer fill requirements. In this article, we present the design and characterization of a routing architecture that allows rule-based automated place and route for both RSFQ and AQFP logic families. We show that a layout tile size of 10 × 10 μm can be designed to accommodate all design rules for layout fill densities, passive transmission line routing, bias current distribution, and the vias needed to stitch multiple ground planes and provide shielded signal and bias tracks. We also characterize the performance of the layout architecture in terms of transmission line parameters and bias current coupling with powerful simulation tools developed for the SuperTools project. The result is a track layout that doubles as chip fill, is now used for integrated circuit layout under SuperTools and is also applicable to any similar fabrication process with at least eight superconductor metal layers.