Methods for testing path delay and static faults in RSFQ circuits

Abstract

Superconducting electronics (SCE), especially Rapid Single Flux Quantum (RSFQ) logic, is being developed due to its high-performance and low power. In [1] [2], we developed new static and delay fault models and an automatic test pattern generator (ATPG) for path delay faults in RSFQ logic. Here we develop a method for selecting path delay faults by identifying the subset of paths for which the delay can exceed the clock period under the main cause of delay faults for RSFQ, namely extreme process variations. We show that this dramatically reduces the number of delay tests required due to the characteristics of gate-level pipelined design, a necessary requirement for RSFQ. We also extend our method to be the first ATPG to generate tests for RSFQ-specific static fault models derived in [1]. We demonstrate that our new ATPG achieves very high coverage of static and delay faults with small numbers of patterns.