Level Shifter Research Articles

High-speed voltage level-up shifter with wide range conversion for system-on-chip applications

Abstract The purpose of this investigation is to demonstrate a level shifter circuit that enhances voltage switching capacity while simultaneously reducing latency by employing a cascaded current mirror, input, and output inverters. We improved our design using multi-threshold Complementary metal oxide semiconductor (MTCMOS) technology by adding stackable transistors, super-cutoff mechanisms, and cascaded techniques. The level shifting between voltage ranges of 0.3 V and 2.0 V is accomplished by the proposed level shifter. Our design has been fine-tuned to meet the needs of system-on-chip applications by meticulously optimizing performance characteristics like energy usage, latency, and space utilization. The proposed level shifter has an area of 6.936 µm2 and a power consumption of 17 nW, with a delay of 90.64 ps. The proposed work has been done on the Cadence Virtuoso Tool using 45 nm technology. Our suggested level shifter is more effective than earlier methods in terms of latency and conversion range. In addition to delivering considerable reductions in space and power consumption, the suggested design promises a 50-fold increase in operating speed.

A Novel Radiation-Hardened Level Shifter With dV/dt Noise Immunity for 600-V HVIC

A Novel Radiation-Hardened Level Shifter With <i>dV</i>/<i>dt</i> Noise Immunity for 600-V HVIC

Full-Swing Nanosecond Delay Hybrid Level Shifter for Time-Critical Applications

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid LS is proposed in this paper, which is a combination of the current mirror LS and cross-coupled LS with a swing-aware output inverter. The proposed LS circuit is designed to ensure full swing, static current-free, and limited current-contention level conversions by preserving the benefits of the current mirror and cross-coupled LS, and using them to eliminate each other’s shortcomings. The proposed hybrid LS is designed and implemented by using 45-nm technology in Cadence Virtuoso tool. Pass transistors and current limiters with multiple thresholds are included for the suggested LS. The proposed LS provides voltage conversion from 0.10 V to 1.20 V. At alevel-shifting voltage of 0.20 V, the proposed hybrid LS at 1 MHz input frequency demonstrates a delay of 8.38 ns, an average power consumption of 3.81 µW, and an energy per transition of 26.64 fJ. Additionally, the suggested LS has low delay, good supply voltage scaling, and delay scalability.

Performance Enhancement of Reduced Component Multilevel Inverter with Optimal Placement of Level Shifter

Performance Enhancement of Reduced Component Multilevel Inverter with Optimal Placement of Level Shifter

An Area and Power Optimization for Level Shifters using 45nm CMOS Technology

Abstract: Modern integrated circuits require level shifters as essential parts to enable communication between circuits running at various voltage levels. Design-wise, the Level Shifter has a minimal silicon footprint due to its limited component count and operates with minimal power usage, making it well-suited for energy-efficient applications. This work implements CMOS voltage level shifter, also known as conventional CMOS level shifter. The level shifter's overall power and area usage are compared. CMOS level shifters simulations are carried out using CADENCE tool. The simulation's outcomes are implemented in conventional 45-µm CMOS technology. Index Terms: Level shifters, - Very Large-Scale Integrated Circuits (VLSI), level shifter, low power

An Ultra Low Voltage Energy Efficient Level Shifter With Current Limiter and Improved Split-Controlled Inverter

An Ultra Low Voltage Energy Efficient Level Shifter With Current Limiter and Improved Split-Controlled Inverter

Monolithically Integrated GaN Power Stage for More Sustainable 48 V DC–DC Converters

In this article, a fully monolithically integrated GaN power stage with a half-bridge, driver, level shifter, dead time and voltage mode control for 48 V DC–DC converters is proposed and analyzed. The design of the GaN IC is presented in detail, and measurements of the single function blocks and the DC–DC converter up to 48 V are shown. Finally, considerations are given on a life cycle assessment with regard to the GaN power integration. This GaN power IC or stage demonstrates a higher level of integration, resulting in a reduced bill of materials and therefore lower climate impact.

A Low-Intensity Pulsed Ultrasound Interface ASIC for Wearable Medical Therapeutic Device Applications

Low-intensity pulsed ultrasound (LIPUS) is a non-invasive medical therapy that has attracted recent research interest due to its therapeutic effects. However, most LIPUS driver systems currently available are large and expensive. We have proposed a LIPUS interface application-specific integrated circuit (ASIC) for use in wearable medical devices to address some of the challenges related to the size and cost of the current technologies. The proposed ASIC is a highly integrated system, incorporating a DCDC module based on a charge pump architecture, a high voltage level shifter, a half-bridge driver, a voltage-controlled oscillator, and a corresponding digital circuit module. Consequently, the functional realization of this ASIC as a LIPUS driver system requires only a few passive components. Experimental tests indicated that the chip is capable of an output of 184.2 mW or 107.2 mW with a power supply of 5 V or 3.7 V, respectively, and its power conversion efficiency is approximately 30%. This power output capacity allows the LIPUS driver system to deliver a spatial average temporal average (SATA) of 29.5 mW/cm2 or 51.6 mW/cm2 with a power supply of 3.7 V or 5 V, respectively. The total die area, including pads, is 4 mm2. The ASIC does not require inductors, improving its magnetic resonance imaging (MRI) compatibility. In summary, the proposed LIPUS interface chip presents a promising solution for the development of MRI-compatible and cost-effective wearable medical therapy devices.

Input Voltage-Level Driven Split-Input Inverter Level Shifter for Nanoscale Applications

A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, which is powered and used at the input stage to achieve maximum conversion efficiency. Layout and simulation results across different corners have demonstrated that the proposed LS is highly useful for cutting-edge nanoscale applications. It can up-convert voltage from 0.2 V to 1.2 V and down-convert from 1.2 V to 0.2 V @ 1 MHz input pulse, with a level-up or level-down mean switching delay of 1.3 ns, and a power of 9.5 nW. Moreover, the LS occupies an area of 8 μm2, which is a reasonably compact size compared to the typical LS designs. Overall, the proposed voltage LS design is an efficient and effective solution that could have an ample range of applications in IoT and biomedical, wireless sensor networks.

Low-power filter design using quasi-floating gate and level shifter approaches for biological healthcare applications

This paper proposes a 4th-order class-AB low-pass filter (LPF) for wearable biological healthcare applications designed by cascading two 2nd-order LPFs. The proposed class-AB LPF uses quasi-floating gate (QFG), flipped source follower (FSF) and level-shifter (LS) techniques to boost its performance. The LPF is designed and validated in CMOS 180 nm technology which emulates the post-layout gain of −0.212 dB, bandwidth of 100 Hz, dynamic range (DR) of 50.26 dB, total harmonic distortion (THD) of −52.5 dB and figure of merit (FOM) of 1.71 × 10-15 J. The class-AB QFG FSF LPF consumes power and area of 0.224 nW and 0.0196 mm2, respectively. Furthermore, the statistically determined coefficient of variation for proposed LPF with 1000 iterations for gain is −0.035, THD is −0.172 and DR is 0.04, respectively. The class-AB QFG FSF LPF is compared with other LPFs which establishes its advantage in terms of low-power consumption and least figure of merit thus confirming its suitability for wearable healthcare applications.

A Less-Delay and Wide Conversion-Voltage-Range Level Shifter by Using Switched-Capacitor Technique for Power-Efficiency Health Electronics

A Less-Delay and Wide Conversion-Voltage-Range Level Shifter by Using Switched-Capacitor Technique for Power-Efficiency Health Electronics

A 500-V, 6.25-MHz GaN-IC With Gate Driver and Level Shifter for Off-Line Power Supplies

A 500-V, 6.25-MHz GaN-IC With Gate Driver and Level Shifter for Off-Line Power Supplies

New, Fast, High-Performance Level Shifter for Buck DC-DC Converter in 180nm CMOS Technology

To reduce power dissipation, the dual supply voltage approach is required for analog circuits in the on-chip integrated circuits. In this paper, a novel circuit of the level shifter for Buck DC-DC Converter using cross-coupled configuration is presented. The proposed work of this paper uses this level shifter to converter voltage of 1.8V to 5V at 180 nm CMOS Technology in Cadence Virtuoso Tool. The propagation delay, energy/transition, and static power were 182.42pS, 0.01 fJ/Transition, and 6 fW, respectively. The final design area is only 60.142 μm2.

Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications

In modern integrated circuits (ICs), the near threshold voltage (NTV) regime has gained significant attention due to its potential for enabling energy-efficient and high-performance designs. Voltage level shifters (VLS) play a crucial role in facilitating signal transmission between different voltage domains, ensuring compatibility and reliable operation of ICs. However, the unique challenges posed by near threshold voltage operation necessitate a careful analysis and design of voltage level shifters to mitigate the impact of process variations, supply voltage fluctuations, and other performance limitations. This paper presents, a novel energy efficient voltage level shifter design for NTV regime. We validated the proposed VLS in an industrial 65 nm CMOS technology and ASAP7 7 nm Fin-Fet technology. The post layout parasitic extracted simulations highlight that the proposed VLS, an average improvement of ∼50 %, 37 % and 67 % in propagation delay, power dissipation and layout area, respectively, is obtained over the recently reported VLS design at a VDD = 0.4 V in 65 nm CMOS technology. At ASAP7 7 nm Fin-Fet technology, the proposed design shows an average improvement of ∼52 % and 29 % in propagation delay and power dissipation, respectively over the recently reported VLS design at VDD = 0.3 V. The proposed VLS design offers a compelling solution for achieving high-performance, energy-efficient designs in low-power applications.

A Sub-1 ppm/°C dual-reference small-area bandgap reference comprising an enhanceable piecewise curvature compensation circuit

This paper presents a low-temperature coefficient (TC) dual-reference CMOS bandgap reference (BGR) for high-performance systems working under a wide temperature range. It consists of a correction approach to eliminate the high-order inaccuracy, in which an enhanceable curvature compensation circuit is adopted to extend the operating temperature range and generate reference voltages with sub-1 ppm/°C TC. In addition, a voltage level shifter (VLS) is used to generate the latter compensated reference voltage but no need for an additional compensation circuit. The proposed BGR designed in a 0.18-µm CMOS process has a simulated TC of 0.75 ppm/°C and 0.28 ppm/°C for the first and second reference outputs, respectively, over a wide temperature range of −50 °C to 130 °C. The proposed BGR occupies a 0.0079-mm2 silicon area. The overheads make the BGR appropriate to provide reference voltages in diverse chips with high-precision systems.

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique

A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA’s DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at −30 to 120 °C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/°C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.

A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

This paper presents a high-speed level shifter with about 500 V/ns power supply slew immunity. In this designed structure, a narrow pulse-controlled current source is adapted to accelerate the voltage conversion and reduce the power consumption. A Fast-Slewing Circuit speeds up the operation of the level shifter based on the current comparison principle. Edge detection technology is used to filter the generated voltage noise and achieve high dV/dt immunity. The proposed level shifter simulated with the 0.18 μm BCD (bipolar-CMOS-DMOS) process shows fast responses with a typical delay of 1.49 ns and 500 V/ns dV/dt immunity in the 200 V high-voltage application, which only occupies a 0.022 mm2 active area with the 0.18 μm BCD process.

A Bootstrap Drive and Level Shifting Method for Buck-boost Converter with NMOS as the Main Switch Transistor

In the design of DC-DC power supply, compared with a P-type metal oxide semiconductor field effect transistor (PMOS) with the same width-to-length ratio, N-type metal oxide semiconductor field effect transistor (NMOS) as the main switching transistor greatly reduces the on-off loss and improves the conversion efficiency of the system. This article introduces a gate voltage bootstrap and level shifter circuit for a Buck-Boost DC-DC converter with NMOS main switching transistor. The drive voltage between the gate and the source pole of the main switch transistor can be stabilized, which is independent of the switch junction voltage (V SW) and solves the problem that the drive voltage of the gate is too high or too low due to the influence of the bootstrap voltage in the traditional structure. Based on the 0.18 μm BCD process, the circuit design and physical implementation of the proposed method are verified. The test results show that the bootstrap drive circuit functions normally and the bootstrap drive voltage is about 5 V when the input voltage is 2.9~4.5 V and the output voltage is −2~-5 V. In addition, the proposed gate-level shifting circuit can reduce the drive delay of the main switch transistor to less than 12 ns.

A microfluidic transistor for automatic control of liquids

Microfluidics have enabled notable advances in molecular biology1,2, synthetic chemistry3,4, diagnostics5,6 and tissue engineering7. However, there has long been a critical need in the field to manipulate fluids and suspended matter with the precision, modularity and scalability of electronic circuits8–10. Just as the electronic transistor enabled unprecedented advances in the automatic control of electricity on an electronic chip, a microfluidic analogue to the transistor could enable improvements in the automatic control of reagents, droplets and single cells on a microfluidic chip. Previous works on creating a microfluidic analogue to the electronic transistor11–13 did not replicate the transistor’s saturation behaviour, and could not achieve proportional amplification14, which is fundamental to modern circuit design15. Here we exploit the fluidic phenomenon of flow limitation16 to develop a microfluidic element capable of proportional amplification with flow–pressure characteristics completely analogous to the current–voltage characteristics of the electronic transistor. We then use this microfluidic transistor to directly translate fundamental electronic circuits into the fluidic domain, including the amplifier, regulator, level shifter, logic gate and latch. We also combine these building blocks to create more complex fluidic controllers, such as timers and clocks. Finally, we demonstrate a particle dispenser circuit that senses single suspended particles, performs signal processing and accordingly controls the movement of each particle in a deterministic fashion without electronics. By leveraging the vast repertoire of electronic circuit design, microfluidic-transistor-based circuits enable fluidic automatic controllers to manipulate liquids and single suspended particles for lab-on-a-chip platforms.