Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications

Abstract

In modern integrated circuits (ICs), the near threshold voltage (NTV) regime has gained significant attention due to its potential for enabling energy-efficient and high-performance designs. Voltage level shifters (VLS) play a crucial role in facilitating signal transmission between different voltage domains, ensuring compatibility and reliable operation of ICs. However, the unique challenges posed by near threshold voltage operation necessitate a careful analysis and design of voltage level shifters to mitigate the impact of process variations, supply voltage fluctuations, and other performance limitations. This paper presents, a novel energy efficient voltage level shifter design for NTV regime. We validated the proposed VLS in an industrial 65 nm CMOS technology and ASAP7 7 nm Fin-Fet technology. The post layout parasitic extracted simulations highlight that the proposed VLS, an average improvement of ∼50 %, 37 % and 67 % in propagation delay, power dissipation and layout area, respectively, is obtained over the recently reported VLS design at a VDD = 0.4 V in 65 nm CMOS technology. At ASAP7 7 nm Fin-Fet technology, the proposed design shows an average improvement of ∼52 % and 29 % in propagation delay and power dissipation, respectively over the recently reported VLS design at VDD = 0.3 V. The proposed VLS design offers a compelling solution for achieving high-performance, energy-efficient designs in low-power applications.