Level Shifter Research Articles

An Automotive-Grade Monolithic Masterless Fault-Tolerant Hybrid Dickson DC–DC Converter for 48-V Multi-Phase Applications

Autonomous-driving features necessitate a fault-tolerant (FT) power-management unit in 48-V automotive applications. This article presents a monolithic single-phase closed-loop masterless FT four-to-one hybrid Dickson converter IC for high-conversion-ratio 48-V automotive multi-phase applications. The chip includes: 1) a mixed-signal droop-based valley-current ON-time quasi-fixed-frequency control, which enables masterless multi-phase operation capability; 2) single-point short-circuit fault and open-circuit fault detection and blocking of any power switches or flying capacitors; 3) an optimized high-voltage (HV) power stage with fully integrated flying-capacitor-sourced gate drivers without any external bootstrap capacitors; 4) a glitch-free cross-coupled bootstrapped HV level shifter; and 5) a dual-leg bidirectional closed-loop current-sensing circuit optimized for the hybrid Dickson topology. The design was fabricated in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> 90-V automotive silicon-on-insulator (SOI) bipolar-CMOS–DMOS (BCD) process. The measured results confirm the operation over 20–60-V input, 3.3-V nominal output, 3-A maximum load, and 320-kHz effective switching frequency within the automotive-grade −40 °C–+125 °C ambient temperature. The design achieves above 90% measured efficiency at maximum conversion ratio and load at room temperature. A three-phase system is used to evaluate and confirm the fault-blocking capability and continuous power delivery upon detection of a fault.

A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller

AbstractDistributed arithmetic (DA) is an efficient way to implement sum‐of‐product units, which can be used in applications such as FIR filters, filter banks, image processing, and convolutional neural networks in IoT hardware accelerators. In this paper, a low‐power architecture is offered centered on two key steps, coarse‐grain power‐performance partitioning and fine‐grain separated power supply, and tuned a level shifter in any digital systems implemented based on RTL design. To examine the new design approach, two methods are proposed, at first exploring the power consumption and critical delay path and then separating the power supply of datapath and controller in DA with/without utilizing an implicit level shifter. To investigate power consumption and timing parameters, two 5‐tap and 16‐tap FIR‐filters are implemented in 65‐nm CMOS standard technology. In proposed1, dynamic and static power consumption of 16‐tap (5‐tap) FIR‐filter is improved by 30% (15%) and 59% (59%), respectively. Nevertheless, the delay and slope of the generated signal in the shiftreg are significantly increased by reducing the power supply. To tackle this issue, the second method suggested with 26% (14%) improvement in dynamic power and 55% (58%) in static power consumption, which does not increase any delay in the output of shiftreg compared to conventional DA‐based FIR filter with solitary power supply.

A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

Design of low power SRAM- based ubiquitous sensor for wireless body area networks

Purpose Smart ubiquitous sensors have been deployed in wireless body area networks to improve digital health-care services. As the requirement for computing power has drastically increased in recent years, the design of low power static RAM-based ubiquitous sensors is highly required for wireless body area networks. However, SRAM cells are increasingly susceptible to soft errors due to short supply voltage. The main purpose of this paper is to design a low power SRAM- based ubiquitous sensor for healthcare applications. Design/methodology/approach In this work, bias temperature instabilities are identified as significant issues in SRAM design. A level shifter circuit is proposed to get rid of soft errors and bias temperature instability problems. Findings Bias Temperature Instabilities are focused on in recent SRAM design for minimizing degradation. When compared to the existing SRAM design, the proposed FinFET-based SRAM obtains better results in terms of latency, power and static noise margin. Body area networks in biomedical applications demand low power ubiquitous sensors to improve battery life. The proposed low power SRAM-based ubiquitous sensors are found to be suitable for portable health-care devices. Originality/value In wireless body area networks, the design of low power SRAM-based ubiquitous sensors are highly essential. This design is power efficient and it overcomes the effect of bias temperature instability.

Power module stray inductance extraction: Theoretical and experimental analysis

We propose a stray inductance extraction method on power modules of the few-kilovolts/several-hundred-amperes class using only low voltages and low currents. The method incorporates a double-pulse generator, a level shifter, a switching device, and a load inductor. The conventional approach generally requires a high voltage of more than half the power module's rated voltage and a high current of around half the rated current. In contrast, the proposed method requires a low voltage and low current environment regardless of the power module's rated voltage because the module is measured in a turn-off state. Both theoretical and experimental results are provided. A physical circuit board was fabricated, and the method was applied to three commercial power modules with EconoDUAL3 cases. The obtained stray inductance values differed from the manufacturer-provided values by less than 1.65 nH, thus demonstrating the method's accuracy. The greatest advantage of the proposed approach is that high voltages or high currents are not required.

Trends in Design of Low Power Circuits Using Level Shifting Buffers for Multi Supply Systems

Power and performance efficiencies are the most important design parameters in system – on - chip design. Numbers of methods were developed for reducing the power and delay by reducing supply voltage and multi supply voltages. Multiple supply voltage designs need voltage level conversions between multiple voltage domains. This is achieved by the application of voltage level shifter (LS) circuits. LSs are an interfacing circuit which interconnects low core voltage to high core voltage and vice versa. LS ease communication among diverse modules. However literature reported that the conventional LSs suffer from delay variation due to dissimilar current driving transistors along with high power dissipation. This paper presents the identification of limitations and design aspects of existing LSs through an extensive literature survey and to project the current state of LSs. This study concentrates on multiple supply voltages, power consumption, and speed of processing in ICs. The detailed literature review is expected to pave way for addressing the issues and challenges related to LSs and helps in design and development of efficient low-power multivoltage LSs in the design aspects of VLSI circuits.

Development of single channel EEG Acquisition system for BCI applications

Brain-Computer Interface (BCI) plays a major role in current technologies such as rehabilitation, control of devices, and various medical applications. BCI or brain-machine interface provides direct communication between a brain signal and an external device. In this paperwork, a detailed survey was carried out with the design of single-channel EEG system for various applications. Also, this paper mainly focused on the development of single-channel electroencephalography (EEG) signal acquisition system which includes a preamplifier, bandpass filter, post-amplifier and level shifter circuits. The design of the preamplifier and post-amplifier circuit was carried out by integrated circuits (IC) such as instrumentation amplifier IN128P and bandpass filter with the help of low power operational amplifier LM324. The developed single-channel acquisition board was tested by acquiring an electrooculogram (EOG) signal with closed and opened eye conditions. The acquired signal is displayed and stored in the computer with the help of the HBM-DAQ unit.

Design Techniques of Sub-ns Level Shifters With Ultrahigh dV/dt Immunity for Various Wide-Bandgap Applications

In high-frequency gate drivers, especially for wide-bandgap applications, hundreds of voltages per nanosecond noise would be generated. Therefore, the sub-ns delay level shifter with high dV/dt immunity is necessary for signal conversion among different voltage domain areas. This article presents design techniques for the sub-ns delay level shifter with ultrahigh dV/dt immunity. The propagation delay of the proposed floating level shifter is dramatically reduced by utilizing the edge detection technique. In order to further improve the performance, auxiliary pull-up circuit, promoting delay matching, and self-calibration techniques are adopted, which make the proposed level shifters more suitable for high-frequency wide-bandgap applications. The level shifter is fabricated in a 0.5 μm bipolar CMOS DMOS (BCD) process, whose results demonstrate the final level shifter achieves zero static power consumption, a 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, and dV/dt immunity up to 250 V/ns. The measurement results show that the sub-ns delay level shifter can be realized, and the minimum delay is only 664 ps at VSSH 25 V. Its figure of merit is just 0.044 ns/(μm × V), which is optimal among previous level shifters. The level shifters are also simulated at the 0.18 μm BCD process, and the propagation delay can be decreased by more than 60%.

High-Speed Dynamic Level Shifter for High-Side Bootstrapped Gate Driver in High-Voltage Buck Regulators

Considering the high-voltage dc-dc buck regulator applications, a high-speed dynamic level shifter for high-side bootstrapped gate driver is presented. By introducing an instantaneous dynamic current, the propagation delay of the level shifter is reduced to 0.25 ns for the high-side switch. The dV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{SW}/dt$ </tex-math></inline-formula> immunity and reliability are improved by a clamp circuit during the positive and negative slewing. The maximum dV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{SW}/dt$ </tex-math></inline-formula> that the proposed circuit can tolerate is up to 18V/ns. The process variation immunity is also enhanced by optimizing the design of bias current generator. The achieved area-efficient level shifter is designed based on thin gate-oxide transistors that are widely used in high-voltage process. Experimental results show that the fabricated regulator with the proposed scheme regulates well with an 18 V input, 3.3 V output, and 2 A load current.

Preparation of a Simple Electrochemical Voltammetry Implementation System

Cyclic Voltammetry is an Electro-chemical process used in the development Energy Storage cells and general electrochemistry. In this report we present the use of an Atmega 326 microcontroller to prepare a Cyclic Voltammetry (CV) implementation system. The modular design incorporated a software pulse - width - modulated triangular wave generator, level shifter circuits, a three - electrode electrochemical tank driver circuit and PLX-DAQ-Excel digital Data Acquisition system. The system measured a 266.1 Ω carbon resistance as 262.7 Ω. It also effectively isolated the cathodic redox potential peak (750 mV) and anodic peak (520 mV) of a 1.5 mM Potassium Ferricyanide in 0.1M Potassium Nitrate at room temperature. A specific capacitance of 11.45 F/g was obtained for a 4.4 cm 2 coconut shell derived screen printed activated carbon electrode. The design is suitable for basic CV studies in Electrical Energy Storage Devices development. Keywords: Microcontroller, Cyclic Voltammetry, Potentiostat, Level – shifter circuits, Potassium ferricyanide, Energy Storage Devices. DOI: 10.7176/JNSR/12-18-04 Publication date: September 30 th 2021

High throughput SRAM design for improved computing in autonomous systems

PurposeHigh throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.Design/methodology/approachPower efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.FindingsBias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.Originality/valueThe proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

Design and Implementation of IoT based flood alert monitoring system using microcontroller 8051

In the Internet of Things (IoT) the physical objects network is described as “things” linked to sensors, software and other technologies to connect and share information through the Internet with other devices and systems. The floods lead to large losses of life and property in several countries. However, the absence of sufficient technology results in further death and property losses as a result of flooding in developed countries. This is because of a lack of flood alert systems. The objective of this paper is to monitor the flood situation and provide a text message warning in the event of a threat. The main aim of this paper is to detect rising river water levels at a safe distance away from the railways and to allow the respective authorities to take appropriate measures by means of SMS. A sensor is a system that senses and reacts to certain physical data. The 8051 microcontrollers were produced by Intel in 1981. The microcontroller is 8-bit. It has 40 DIP pins, 4 kb of ROM stores and 128 bytes of RAM and two timers and 16 bits. It is equipped with 2 timers. There are four parallel 8-bit ports that are programmable and adjustable as necessary. The hardware device that uses GSM mobile technology for the provision of an information link with a remote network is a GSM modem or a GSM module. A float switch is a level sensor type, a fluid control system that is used inside a tank. A condenser is a tool that stores electrical energy in an electric field. It's a passive electronic feature with two terminals. A LED is a semiconductor light source that transmits light through the flowing current. Liquid Crystal Display stands for LCD. It is a thin, flat display device used in a variety of electronics. A digital electronic level shifter is a system used in the transformation of signs from one logic or voltage domain to another, also known as logic level shifter or voltage level Translation. A diode is an electronic component with a two-terminal that mainly conducts current in one direction, with low resistance and high resistance in one direction. The aim of this paper is to detect early Flood and give early warnings to Needy people.

Fermi Level Equilibration at the Metal-Molecule Interface in Plasmonic Systems.

We highlight a new metal-molecule charge transfer process by tuning the Fermi energy of plasmonic silver nanoparticles (AgNPs) in situ. The strong adsorption of halide ions upshifts the Fermi level of AgNPs by up to ∼0.3 eV in the order Cl- < Br- < I-, favoring the spontaneous charge transfer to aligned molecular acceptor orbitals until charge neutrality across the interface is achieved. By carefully quantifying, experimentally and theoretically, the Fermi level upshift, we show for the first time that this effect is comparable in energy to different plasmonic effects such as the plasmoelectric effect or hot-carriers production. Moreover, by monitoring in situ the adsorption dynamic of halide ions in different AgNP-molecule systems, we show for the first time that the catalytic role of halide ions in plasmonic nanostructures depends on the surface affinity of halide ions compared to that of the target molecule.

FPGA Data Acquisition of Electrical Parameter

A data acquisition system using a Programmable Logic Gate Array (FPGA) and Graphical User Interface (GUI) for visual enhancement designed for Personal Computer is shown. The data acquisition of voltage (V), current (A) and temperature ( ) signals and/or parameters transmitted at high frequency in real time via the system-on-chip (SOC) created on Spartan 6 FPGA. The system-on-chip is achieved by programming the FPGA with a high-speed hardware description language (Verilog) code written for the system, Printed Circuit Board (PCB) was designed for the system and the GUI has been created using a graphical approach utilizing LabVIEW to enable data monitoring on Personal Computer (PC) display. The FPGA requires digital input signals; therefore, an analogue to digital convertor (ADC) is required for the convert sensor data from analogue signal from sensors to digital signals. A voltage level shifter is required to normalise the voltage level standards within the circuity in between the 5V from the ADC converter and the 3.3V voltage requirement for the FPGA. The Spartan 6 FPGA receives data from the analogue sensors via the ADC, the data are wrapped up in packets and transmitted through RS-232 serial port to the PC. The three aforementioned parameters are monitored on the GUI on the PC presented in both numerical and graphical format and all data can be store in a file for backup storage, maintenance or reference purposes.

FPGA Data Acquisition of Electrical Parameter

A data acquisition system using a Programmable Logic Gate Array (FPGA) and Graphical User Interface (GUI) for visual enhancement designed for Personal Computer is shown. The data acquisition of voltage (V), current (A) and temperature ( ) signals and/or parameters transmitted at high frequency in real time via the system-on-chip (SOC) created on Spartan 6 FPGA. The system-on-chip is achieved by programming the FPGA with a high-speed hardware description language (Verilog) code written for the system, Printed Circuit Board (PCB) was designed for the system and the GUI has been created using a graphical approach utilizing LabVIEW to enable data monitoring on Personal Computer (PC) display. The FPGA requires digital input signals; therefore, an analogue to digital convertor (ADC) is required for the convert sensor data from analogue signal from sensors to digital signals. A voltage level shifter is required to normalise the voltage level standards within the circuity in between the 5V from the ADC converter and the 3.3V voltage requirement for the FPGA. The Spartan 6 FPGA receives data from the analogue sensors via the ADC, the data are wrapped up in packets and transmitted through RS-232 serial port to the PC. The three aforementioned parameters are monitored on the GUI on the PC presented in both numerical and graphical format and all data can be store in a file for backup storage, maintenance or reference purposes.

Contention Mitigation based Level Shifter Architecture

Energy efficiency is one of the most important issues that needs to be solved in the current system on chip design. To overcome this issue, many circuits inside the chip run at low power. However there are some blocks like memories that run at relatively higher voltages. This means, modern day SOC contains different voltages running through it. The problem arises when two blocks operating at different voltages want to communicate with each other. This problem is solved by using Level Shifters as an interfacer between the blocks. The function of Level Shifter is to convert voltage level of input signal to that of the output. In this paper a cross coupled architecture of Level Shifter is proposed which operates between 1.5v and 5v. The speciality of this architecture is there is less contention between pull up network and pull down network, which reduces the rise and fall delay significantly. The proposed design is simulated at different operating conditions and the functionality is checked.

An efficient high speed and low power voltage-level shifter

This study proposes a novel negative level shifter capable of converting low levels of input voltages to high output voltages while maintaining high speed and low delay and superior static power dissipation. The proposed level shifter is composed of a combination of cross-coupled and current mirror configurations. The minimal operating voltage of the proposed level shifter is 400mV. In addition to the operating range, the power consumption and delay of the proposed level shifter were designed for low-power applications. Under VDDL=0.4V, VDDH=1.8V and fin=1MHz condition, the average power, energy/transition and static power were 2.6μW,26fJ/Transition, and 70pW, respectively.

A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques

Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review of CMOS Current mirrors and their techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell

The paper presents a class-AB flipped voltage follower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/output voltage swing and low output resistance. In the proposed FVF cell, the level shifter increases the input/output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in low output resistance. The proposed FVF cell offers wide input/output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and low output resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.