An Area and Power Optimization for Level Shifters using 45nm CMOS Technology

Abstract

Abstract: Modern integrated circuits require level shifters as essential parts to enable communication between circuits running at various voltage levels. Design-wise, the Level Shifter has a minimal silicon footprint due to its limited component count and operates with minimal power usage, making it well-suited for energy-efficient applications. This work implements CMOS voltage level shifter, also known as conventional CMOS level shifter. The level shifter's overall power and area usage are compared. CMOS level shifters simulations are carried out using CADENCE tool. The simulation's outcomes are implemented in conventional 45-µm CMOS technology. Index Terms: Level shifters, - Very Large-Scale Integrated Circuits (VLSI), level shifter, low power