Development of compact voltage level-up shifter for nano-second delay system-on-chip applications

Abstract

The Level Shifter is made with two inverters and a Wilson current mirror to use less energy. In order to reduce the amount of leaking power, this study suggests using a combination of super-cut-off draw-down and stacked pull-up networks. The design also incorporates multi-threshold complementary-metal-oxide-semiconductor (MTCMOS) technology, which, consists of sleeper transistors that are able to boosts performance without increasing either power usage or size. The designed device can be used to shift voltage in between 0.4 V and 1.2 V. To suit nano-scale uses, the circuit’s operating range and performance factors (such as power, latency, and area) were fine-tuned. According to the results, ‘level-up’ transitions typically consume 148.6nW of active power and have an average delay of 1.19 ns at 1 MHz transmission rates. The post-layout model indicated that the recommended plan would need 9.47 μm2 of floor space. The results are analyzed in Cadence Virtuoso using 45 nm techniques.