Leakage Energy Research Articles

A Quintupler Boost High Conversion Gain Soft-Switched Converter for DC Microgrid

This study proposes a high conversion gain soft-switching quintupler boost non-isolated converter for DC microgrid. By inclusion of quintupler rectifier and coupled inductor with reduced duty cycle, high voltage gain is obtained. The leakage energy of coupled inductor is recycled through an auxiliary switch and the output capacitor improves further boost. Due to the active clamp and this recycled leakage energy, huge inductive voltage spikes across MOSFETs are alleviated and also, stress is reduced. Hence, low voltage rating (low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{ds(ON)}$ </tex-math></inline-formula> ) switches can be utilized and minimize conduction losses. In addition, this clamp enables zero-voltage switching (ZVS) for both the MOSFETs, even at light loads. Quintupler multiplier rectifier reduces the voltage stress across diodes. This, in turn, reduces reverse recovery losses for multiplier diodes. Further, the coupled inductor leakage inductance in series with diodes provides for the snubbing effect to alleviate voltage spikes across quintupler diodes. Thus, the overall diode voltage rating reduces. This improves power density and improves the overall efficiency of the converter. Finally, a 400W prototype operates at 100kHz is developed to validate the converter performance. The measured peak efficiency is 96.43%.

A Single-Switch High Step-Up DC–DC Converter Based on Three-Winding Coupled Inductor and Pump Capacitor Unit

In this article, a novel single-switch, high step-up dc–dc converter based on three-winding coupled inductor and voltage multiplier circuit (VMC) is proposed. And on this basis, pump capacitor unit (PCU) is integrated to achieve a very high voltage gain. The converter makes full use of the advantages of three-winding coupled inductor, skillfully combines it with the VMC, and integrates the PCU that can be used in superposition to further improve the voltage gain. The voltage stress of the switch is reduced by using a passive clamping circuit to recycle the leakage energy of the coupled inductor. The operating principle and steady-state analysis of the presented converter in continuous conduction mode are introduced in detail. Moreover, the comparative analysis shows that under the same conditions, the proposed converter has higher voltage gain and lower voltage stress than others. Several advantages include high voltage gain, low voltage stress, low turns ratio of coupled inductor, and high conversion efficiency, make the proposed converter very suitable for new energy generation applications, such as photovoltaic systems. Finally, the feasibility of the proposed converter and the correctness of theoretical analysis are verified by a 500-W prototype at 50 kHz switching frequency.

Cascaded-like High-Step-Down Converter with Single Switch and Leakage Energy Recycling in Single-Stage Structure

A cascaded-like high-step-down converter (CHSDC) is proposed in this article, which can steeply convert a high voltage to a much lower level without the utilizing of extreme turns ratio or duty ratio. The proposed converter integrates two buck-boost converters and one forward converter to form a single-stage architecture containing only a single low-side driving switch, which, as a result, can lower the cost and reduce the complexity of the associated control driver. Even in a single-stage single-switch structure, the ability to step down input voltage is as effective as the cascade of two buck-boosts and one forward converter. Meanwhile, the proposed converter can avoid the low efficiency caused by a cascaded structure. Without an additional clamp circuit, the leakage energy stored in the transformer of the CHSDC can be still recycled so as to raise the efficiency of the converter and suppress voltage spikes at the power switch. Converter operation principle and key parameter design are discussed. Moreover, a 200 W prototype is built and then tested to validate the proposed converter and verify the theoretical analysis.

Capacitor Clamped Coupled Inductor Bi-Directional DC-DC Converter with Smooth Starting

In this paper, a new type of capacitor clamped coupled inductor bidirectional DC–DC converter is proposed, which offers high voltage gain with smooth starting current transients, as well as reduced stresses on the capacitor. Steady state operation, mathematical modelling, and state space modelling for the proposed converter are presented in detail. A simplified single voltage clamped circuit is developed to mitigate the voltage spikes caused due to the coupled inductor by recovering the leakage energy effectively. Moreover, the clamping capacitor helps in reducing the ripples in output voltage, which in effect significantly reduces the stress on the switch and offers less ripple content at the load terminals. Simulation of the proposed converter is carried out using Simulink/MATLAB for the conversion of 24V DC to 200V DC. For this conversion, simulation results have proven that there is reduction of 13.64% of capacitor voltage stresses. Further, under line varying conditions, converter responses have proven that there is a 119% and 25.25% reduction in input current and output voltage transients, respectively. Similarly, 25.25% and 76.5% transient reductions of input current are observed for line and control parameter variations. The hardware investigation of the converter was carried out with a 100 W, 24 V/200 V setup. The converter achieved efficiency of 93.8%. The observations supplement the simulation results.

Intelligent Fuzzy Based High Gain Non-Isolated Converter for DC Micro-Grids

Renewable electricity options, such as fuel cells, solar photovoltaic, and batteries, are being integrated, which has made DC micro-grids famous. For DC micro-grid systems, a multi input interleaved non-isolated dc-dc converter is suggested by the use of coupled inductor techniques. Since it compensates for mismatches in photovoltaic devices and allows for separate and continuous power flow from these sources. The proposed converter has the benefits of high gain, a low ripple in the output voltage, minimal stress voltage across the power semiconductor devices, a low ripple in inductor current, high power density, and high efficiency. Soft-switching techniques are used to realize that the reverse recovery issue of the diodes is moderated, the leakage energy is reused, and no new scheme is appropriated. To reduce conduction losses, minimum voltage rating MOSFETs with a low ON-resistance can be utilized. The converter can supply the required power from the load in the absence of one or two resources. Furthermore, due to the high gain of boosting voltage, the converter works in an Adaptive Neuro-Fuzzy Inference System (ANFIS). The operation principle, steady-state analysis of the proposed converter, is given and simulated utilizing MATLAB/Simulink simulation software.

ROBUST AND SECURE S-BOX DESIGN WITH GATED HYBRID ENERGY RECOVERY LOGIC (GHERL) FOR IOT APPLICATIONS

The smart Internet of Things (IoT) network relies heavily on data transmission over wireless channels. Hence, it should be designed to be robust against the attacks from hackers and antagonists. The confidentiality in IoT devices is directly proportional to the complexity and power consumption. To mitigate these issues, this paper proposes a secure Substitution Box (S-Box) design that is exploited in the IoT for cyber security applications. The S-Box is based on Gated Hybrid Energy Recovery Logic (GHERL) that is an amalgamation of two different techniques as adiabatic logic and power gating. Adiabatic logic is preferred to attain high energy efficiency in practical applications such as portable and handheld devices. Power gating technique is preferred to reduce the leakage power and energy consumption. The proposed GHERL XOR gate and S-Box are implemented with 125nm technology in Tanner EDA tool. The consequences of the experiments exhibits that the novel S-Box design with GHERL XOR decreases the power consumption by 1.76%, 35.26%, 36.81%, 41.01% and reduces the leakage power by 58.54%, 20.27%, 27.38%, 13.63% when compared with the existing techniques such as S-Box with sleep transistor, dual sleep transistor, dual-stack and sleepy keeper approach. Keywords: Adiabatic logic, Power Gating, Internet of Things, S-Box

New Modulation and Impact of Transformer Leakage Inductance on Current-Source Solid-State Transformer

This article presents a novel modulation scheme for device voltage stress mitigation and comprehensive analysis of the impact of transformer leakage inductance in a current-source solid-state transformer (SST). Different from dual active bridge (DAB) SST, the operation of the current-source SST is similar to that of a flyback converter. The device bridge on only one side of the transformer is active to store energy into or release energy from the magnetizing inductance which acts as a current-source dc-link. Such flyback operations with reverse-blocking switches can lead to additional device voltage stress and incomplete zero-voltage switching (ZVS) on the current-source soft-switching solid-state transformer (S4T) under conventional modulation. A new modulation scheme is proposed to address this issue. Moreover, different from the DAB, the leakage inductance of the medium-frequency transformer (MFT) in the S4T is a parasitic element similar to that in a matrix SST and can cause additional device voltage stress. Though the resonant capacitors, originally added to achieve ZVS, can absorb and recycle the leakage energy in the S4T, these capacitors need to be increased with larger leakage inductances to limit the voltage stress. However, large resonant capacitors can result in more lost duty cycles and reduced efficiency. The impact of such leakage inductance on device voltage stress is analyzed comprehensively, which is critical to guide future research and design of the S4T. Experimental results from S4T prototypes for dc–dc, multiport ac–dc, and ac–ac conversion with 1:1 and 4:1 MFT comprehensively verify the proposed concepts. Finally, a case study of a three-phase ac–ac S4T over a power range from 1 to 100 kVA each module reveals that the MFT leakage inductance should be less than 1% of the magnetizing inductance for safe operation.

Improved Complex Receiver System Design Strategies to Overcome EMI/EMC Challenges

This article analyzes various strategies and implementation techniques in detail for complex receiver system design to qualify Environmental Stress Screening (ESS) especially EMI/EMC tests for airborne system applications. Isolation of leakage energy between various RF/DC-DC converters/regulators/pulsing blocks are the key target of this design to keep conductive and radiative emission to a minimum. Hence, complex receiver design has been segregated into various modules. Then they are stacked together very tactfully within the specified area without compromising inter-channel/module interference between them and the form factor, respectively. The super compact stacks are further channelized for RF, DC supply, controls etc. and protected from any kind of interference. Low cost flexi interconnects are made to interface various stacks to arrest unwanted high/low frequency leakages. Proper layout, component placement, layer specific signal routing, and wire shielding have been used to protect low/high frequency reference clock, control signals, switching pulses, etc. from mixing. Processor boards with a DC supply unit are also integrated into the receiver as another stack and have been isolated from each other to qualify emission tests. Finally, four modules are developed and tested over temperatures of -40°C to +71°C (ESS) and EMI/EMC successfully to establish the methodology for mass production.

Reducing GPU Energy Consumption by Packing Narrow-Width Operands

In this paper, we study the use of an Operand-Width-Aware Register (OWAR) packing mechanism for graphics processing unit (GPU) energy saving. In order to efficiently use the GPU register file (RF), OWAR employs a power gating method to shut down unused register sub-arrays in order to reduce dynamic and leakage energy consumption of RF. As the number of register accesses was reduced due to the packing of the narrow width operands, the dynamic energy dissipation was further decreased. Finally, with the help of RF usage optimized by register packing, OWAR allowed GPUs to support more thread-level parallelism (TLP) through assigning additional thread blocks on streaming multiprocessors (SMs) for general-purpose GPU (GPGPU) applications that suffered from the deficiency of register resources. The extra TLP opens opportunities for hiding more memory latencies and thus reducing the overall execution time, which can lower the overall energy consumption. We evaluated OWAR using a set of representative GPU benchmarks. The experimental results showed that compared to the baseline without optimization, OWAR can reduce the GPGPU’s total energy up to 29.6% and 9.5% on average. In addition, OWAR achieved performance improvement up to 1.97X and 1.18X on average.

A single‐switch high‐gain DC–DC converter for photovoltaic applications

AbstractThis article presents a high‐gain DC–DC converter consisting of a quadratic boost converter and a voltage multiplier, which helps to lift up the voltage gain. The gain will be further enhanced by increasing the turn's ratio of the coupled inductor. The key features include ultrahigh gain, low voltage stress across switching devices, low input current ripple, and hence, it is preferably suitable for renewable energy applications. A passive clamp lowers the voltage stress across MOSFET, so allowing switch with lower Rds(on) reduces the system cost. Besides this, input inductor makes current continuous and reduces input current ripple. The reverse recovery problem of diodes also gets diminished with the usage of leakage energy of the coupled inductor. The operating principle with different modes of operation is also explained. Zero current switching (ZCS) turn‐on is achieved for power switch, and ZCS turn‐off is achieved for diodes, which helps to reduce the switching losses. This improves the overall system efficiency. A 250‐W prototype is built up to validate the converter.

An Improved ZVS High Step-Up Converter Based On Coupled Inductor and Built-In Transformer

A high step-up dc-dc converter with multiple magnetic devices and switched-capacitor voltage multiplier cell (SC VMC) is proposed in this article. By simultaneous implementation of a coupled inductor (CI) and a built-in transformer (BIT), the voltage gain is flexibly increased with an additional degree of freedom in comparison with the converters with only BIT or CI. To further increase the voltage gain, the secondary winding of the CI is inserted in series with the primary winding of the BIT. This new architecture leads to multiplication of the turns ratios of the CI and BIT in the voltage gain expression, as well. The SC VMC not only extends the voltage gain but also reduces the voltage stress across the MOSFETs. To have a better device utilization, the blocking capacitor is participated in voltage gain improvement. Moreover, through active clamp circuit, the leakage energy of the magnetic devices is recycled and zero voltage switching (ZVS) performance is obtained for the main and auxiliary MOSFETs. In such a case, the switching frequency can be increased to reduce the volume of the converter. Finally, a 400-W laboratory prototype with 25- 400 V voltage conversion is fabricated to demonstrate the effectiveness of the proposed converter.

Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

A new non-isolated interleaved high step-up gain DC-DC converter with reduced voltage stress on switching devices

ABSTRACT This paper proposes a new Non-Isolated Interleaved (NII) high step-up gain DC-DC converter. This new topology aimed for high power applications, which achieves high step-up voltage gain without a high turns ratio n and a high duty cycle. This converter comprised of two-phase interleaved Coupled-Inductors (CIs) integrated with voltage multiplier rectifier and switched capacitor. The key feature of this converter is very low voltage stress on switching devices compares to existing NII high step-up gain topologies for the similar gain. The reduced rating allows the use of low-voltage rating power devices. Besides, the presented converter inherently recycles the leakage energy, and do not require an auxiliary clamp circuit. In addition, the switching operation is free from the reverse recovery problem due to the zero-current-switching. The working principle and performance characteristics of the converter are presented in detail. The analytical study of effect of parasitic parameters on voltage gain and efficiency of this converter is also presented. The performance comparisons with existing NII high step-up gain topologies are provided to highlight the merits of the converter. To verify the correctness of the theoretical analysis, the experimental setup of 300 W is built. The experiments are conducted to boost 24 V–380 V with turns ratio n = 1, and to boost 24 V–580 V with n = 2.

Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design

This brief presents a neuromorphic processor with asynchronous routers and configurable LIF neuron models. The neurocore microarchitecture revolves around a high- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> SRAM to reduce leakage, alongside reconfigurable neuron compute logic circuits and async routers to maximize energy efficiency. The neuron compute module achieves low power via an area efficient ALU implementation by using only adder and bitshifter circuits. We describe this LIF neuron model ALU design, and also include key neurocore verification scenarios (i.e., router deadlocks and functional coverage), CPU-neurocore control flow, and asynchronous router performance analysis. Our 16-core fabricated chip in 40 nm CMOS process works down to 0.5V. The measured leakage and average energy efficiency are 0.93 μW/core and 4.8 pJ/SOP respectively (at 0.5V), which is 20% better than state of the art.

Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA

Aims: Embedded system plays a vital role in today’s life. Hence, our interest is in areadelay- energy efficient embedded system design in post-CMOS technology, i.e., QCA. Objectives: The research is focused on efficient area-delay-energy Configurable Logic Block (CLB) design for Field-Programmable Gate Array architecture (FPGA) with successful simulation-based on next-generation technology, Quantum-dot cellular automata. Methods: Each proposed circuit is designed on post CMOS 4 dot 2 electron technology, i.e. QCA (Quantum dot Cellular Automata), is adopted in circuit implementation due to low power dissipation, high clock frequency and high package density. QCADesigner is used to verify the functionality of every circuit. QCAPro tool is used for determining power dissipation. Results: In contrast, a new approach of using de-multiplexer replacing the decoder has been introduced that results in the reduction of the average energy dissipation by almost 57%. A NOR based D flip-flop memory architecture and multiplexer are also used in the lookup table for the configurable logic block. The proposed architecture thus reduces the overall latency. The proposed CLB consists of 6356 QCA cells covering 7.44 um2 area. Write and read latency of proposed CLB are 12 and 7.25 QCA clock, respectively. Conclusion: The present paper concludes that read and write latency reduction occurs; average energy dissipation, leakage, and switching energy dissipation are reduced in a large amount resulting in an advantage of the overall minimization of the latency for the proposed CLB in the process.

Battery Charger Utilizing Coupled Inductor Based High Gain Bidirectional DC-DC Converter: Analysis, Design, and Implementation

The bidirectional dc-dc converter with high voltage gain and high efficiency plays an important role in the designing of battery charging systems. In this paper, design and development of a battery charging system utilizing coupled inductor based high gain dc-dc converter is presented. The converter uses a clamp capacitor network to recover the leakage energy of a coupled inductor. The converter has inherent soft-switching capability during turn ON, which ensures high efficiency at high switching frequency. Design equations to derive value of different passive components are given and a step-wise exclusive design to construct coupled inductor is presented. A 50 kHz, 500 W laboratory prototype has been designed, which can increase the voltage with 10 gain (boost operation) in one direction and can reduce the voltage at (1/10) gain (buck operation) in other direction. The CCCV battery charging algorithm is implemented using generic ARM Cortex-M4 microcontroller. Extensive experiments have been performed and the experimental results are presented in buck, boost, and battery charging operations.

An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance

Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache allows to power it down removing its leakage energy consumption. When multiple programs run simultaneously on multiple cores, small programs bypass the L2 cache while large programs use it. This decreases conflicts in the L2 cache among those programs increasing overall performance. From our experiments using cycle-accurate performance and energy simulators, our proposed L2 cache architecture supporting bypassing is shown to be effective in reducing L2 cache energy consumption and increasing overall performance of programs.

Excellent leakage current performance and energy storage density achieved in Zr-modified Sr0.925Bi0.05TiO3 thin film

In this paper, the leakage current performance and energy storage of Sr0.925Bi0.05Ti1−xZrxO3 (x = 0, 0.05, 0.07 and 0.1) thin films with perovskite structure were investigated. With the increases of x, the leakage current performance and breakdown strength were optimized remarkably, resulting the recoverable energy density of 26.9 J/cm3 at x = 0.1, which is almost double that of Sr0.925Bi0.05TiO3 thin film. The high breakdown strength, low dielectric loss and high recoverable energy density make the thin films a potential candidate for application in energy storage devices.

High Gain and High-Efficiency Bidirectional DC–DC Converter With Current Sharing Characteristics Using Coupled Inductor

Application of coupled inductor in designing nonisolated bidirectional dc-dc converter provides flexibility to attain high voltage conversion ratio both in buck and boost mode of operation. In this article, a new coupled inductor bidirectional converter is designed with low winding turns ratio (n = 1). The proposed topology uses two current path inductor structure which improves voltage conversion ratio and shares current in all operating modes. All the active switches in the proposed topology are soft switched utilizing synchronous rectification concept. Higher efficiency operation is possible as no extra circuit elements are required to achieve soft switching. Leakage energy of coupled inductor is successfully stored in a clamped capacitor which is utilized in the circuit topology. The voltage stress and current stress level of main active switches are low. The proposed circuit is simulated and performance parameters are verified through hardware results. Both simulation and experimental results performed on a 250 W prototype confirm to attain a high efficiency of the proposed converter with simple hardware requirement for practical implementation.

A soft switching four‐phase converter with ultra‐high step down conversion ratio and automatic uniform current sharing

This paper introduces a new high step down four-phase converter with soft switching and automatic uniform current sharing. The phase number of the introduced topology can be expanded. In this converter, the main switches are turned on under zero voltage zero current switching condition and turned off under zero voltage switching. Also, the auxiliary switches and diodes operate respectively under zero voltage switching and zero current switching conditions. In the proposed architecture, the duty cycle is extended and the semiconductors voltage stress is reduced by applying series capacitors and coupled inductors. The leakage energy associated with the coupled inductors is absorbed and the reverse recovery losses of diodes are eliminated. Uniform current sharing between four phases is achieved without any extra current sharing control circuit. Furthermore, by utilizing the interleaved method, the current stress and the output current ripple are reduced. This converter provides above advantages while its input and output grounds are connected. As a result, the introduced topology can provide high step down conversions at high frequencies. The converter operation and its characteristics are analysed in detail. The accuracy of the theoretical analysis is verified by a laboratory prototype.