An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance

Jungwoo Park,Jong-Uk Hou,Soontae Kim

doi:10.3390/electronics10111328

Jungwoo Park, Jong-Uk Hou + Show 1 more

Open Access

https://doi.org/10.3390/electronics10111328

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Abstract

Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache allows to power it down removing its leakage energy consumption. When multiple programs run simultaneously on multiple cores, small programs bypass the L2 cache while large programs use it. This decreases conflicts in the L2 cache among those programs increasing overall performance. From our experiments using cycle-accurate performance and energy simulators, our proposed L2 cache architecture supporting bypassing is shown to be effective in reducing L2 cache energy consumption and increasing overall performance of programs.

Highlights

Multicore processors become popular in mobile systems such as smartphones and smartpads
The L2 cache leakage energy consumption can be reduced entirely when a single program runs and harmonic mean performance can be improved by up to 41.7% when multiple programs run simultaneously
As L2 cache capacity increases, the L2 cache energy consumption increases but other components does not show energy increases. This means that the L2 cache capacity variation does not affect memory and core operations

Summary

Introduction

Multicore processors become popular in mobile systems such as smartphones and smartpads. Several architectural techniques have been proposed to reduce leakage energy consumption of L2 caches using gated-Vdd and drowsy cache schemes They generally try to detect dead cache lines and put them in a low-leakage mode, which, requires applying the gated-Vdd and drowsy cache schemes at cache line granularity, increasing area overhead very much. Due to this reason, recent application processors employed in smartphones support a low-leakage mode at larger granularity, for example at half size of L2 cache granularity [3]

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