Junctionless TFET Research Articles

Design and Analysis of Junctionless Based Symmetric Nanogap-Embedded TFET Biosensor

In the present paper, symmetrical configuration of dual material double gate dielectric modulated junctionless TFET (DM DG JLTFET) for biosensor applications is explored. The JLTFET consists of Si material with an intensely doped n-type substrate. In this work, the JLTFET utilizes the dielectric modulation method which aids the bio-transistor to recognize neutral and charged analytes (biomolecules). A double metal gate structure is designed by employing two dissimilar metal gate electrodes to reduce short channel impact on device characteristics. The proposed device includes a nanogap region (cavity) which is framed for biomolecules to immobilize. Surface potential and their sensitivity are examined for neutral and charged-neutral analytes. The effects of structure parameters such as nanogap region length and fill-in factor have been analyzed through simulation. The paper examines the behavior of DM DG JLTFET for biological molecules sensing via change in relative permittivity and charge density. The proposed device shows noticeable sensitivity results for charged biomolecules (especially for positively charged analytes). The present work has analyzed the different parameters affecting the sensitivity of the biosensor which includes structural geometric variations like change in cavity length, cavity thickness and fill-in factor. The sensitivity of the neutral biomolecules having higher dielectric constant is observed higher; the surface potential sensitivity of the Gelatin (k = 12) is estimated as 3.75 × 10 3 which is 45%, 55%, and 135% higher than the sensitivity of Keratin (k = 7), Bacteriophage T7 (k = 6), and Glucose Oxidase (k = 3), respectively at the cavity length of 7 nm.

Linearity performance analysis of junctionless nanotube tunnel field effect transistor

The article provides linearity performance parameter of junctionless nanotube TFET (JL-NT-TFET) for the application of ultra-low standby power and radio frequency ICs (RFICs). The proposed charge plasma device uses an inner gate with a similar workfunction as the outer gate electrode. The inner gate of the device provides better electrostatic controllability, increases turn-on capability. JL-NT-TFET shows the subthreshold swing of 20.5 mV decade, minimum leakage current, and higher current as compared to junctionless nanowire TFET (JL-NW-TFET). Linearity performance analyzed in terms of VIP2, VIP3, IIP3 and 1-dB compression point. Results obtained from JL-NTTFET is further compared to JL-NW-TFET. Simulation results of both the devices indicate that the JL-NT-TFET shows better linearity performance, hence it can be applied to low power high-frequency applications.

Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: Impact of temperature on RF/linearity performance

This paper addresses the effect of temperature variation on the performance of a novel device structure Si-doped Hf[Formula: see text] negative capacitance junctionless tunnel field effect transistor (Si:Hf[Formula: see text] NC-JLTFET). Here, Si:Hf[Formula: see text] ferroelectric material is deployed as gate stack along with high-K gate dielectric Hf[Formula: see text]. Si:Hf[Formula: see text] ferroelectric material generates NC effect during the device operation. This phenomenon is an effective technique for intrinsic voltage amplification, reduction in power supply, as well as minimization of power dissipation. The proposed device structure has two variants, symmetric and asymmetric with respect to the oxide thickness between electrode and Si body at both drain and source sides. As band-to-band tunneling in TFET is temperature dependent, it is very crucial to analyze the impact of temperature variation on the device performance. This work is mainly focused on investigating the device dc performance parameters, analog/RF performance parameters and linearity performance parameters by observing the impact of temperature variation. The device characteristics reveal that for dc and RF performance parameters, asymmetric structure shows better result. Highest [Formula: see text] ratio and minimum SS are reported as [Formula: see text] and 20.038 mV/dec, respectively, at 300K for asymmetric structure. At elevated temperatures higher cutoff frequency and reduced intrinsic delay project the device as a strong candidate for ultra low-power and high switching speed applications. Further, the reported device shows better linearity performance at higher temperatures.

Electrical performance of InAs/GaAs0.1Sb0.9 heterostructure junctionless TFET with dual-material gate and Gaussian-doped source

In this work, we demonstrate the design of a dual-material gate and Gaussian-doped source heterostructure junctionless tunnel field-effect transistor (DMG-GDS-HJLTFET). Unlike the conventional dual-material gate heterostructure junctionless tunnel field-effect transistor (DMG-HJLTFET), the proposed structure uses a Gaussian-doped source and adopts InAs/GaAs0.1Sb0.9 as a heterojunction at the source and channel interface, where a polarization electric field is induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 Zinc blende crystal. At the same time, the control gate electrode of the proposed structure is divided into two parts, namely tunnel gate (TG) and auxiliary gate (AG). In this structure, TG is located near the source side and has a lower work function, while AG is located near the drain side and has a higher work function, which not only improves ON-state current (Ion) but also decreases the OFF-state current. The performance of the proposed device is analyzed and compared with that of DMG-HJLTFET; simulation results show improvements in Ion, subthreshold swing, transconductance (gm), cut-off frequency (fT) and gain bandwidth (GBW). Compared with conventional DMG-HJLTFET, the maximum Ion and gm of the DMG-GDS-HJLTFET are 4.1 × 10−4 A μm−1 and 1.27 × 10−3 S μm−1 at 1.2 V gate-to-source voltage (Vgs); further, average subthreshold swing of DMG-GDS-HJLTFET is only 13.6 mV Dec−1 at low drain voltages. Also, DMG-GDS-HJLTFET could obtain a maximum fT of 193 GHz at Vgs = 0.8 V and a maximum GBW of 55.7 GHz at Vgs = 1.12 V, respectively.

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunneling (BTBT) rate, and introduce a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current. Simultaneously, to further decrease ambipolar current, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, respectively, where ΦM1 = ΦM3 < ΦM2. Simulation results indicate that DMMG-HJLTFET provides superior performance in terms of logic and analog/RF as compared with other possible combinations, the ON-state current of the DMMG-HJLTFET increases up to 9.04 × 1 0 − 6 A/μm, and the maximum gm (which determine the analog performance of devices) of DMMG-HJLTFET is 1.11 × 1 0 − 5 S/μm at 1.0V drain-to-source voltage (Vds). Meanwhile, RF performance of devices depends on the cut-off frequency (fT) and gain bandwidth (GBW), and DMMG-HJLTFET could achieve a maximum fT of 5.84 GHz, and a maximum GBW of 0.39 GHz, respectively.

Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology

This work proposed the design of low power Si0.7Ge0.3 pocket Junction-less TFET (JLTFET) on bulk silicon using below 5 nm technology. The inclusion of junction-less regions improves ON-state current with lesser effect on OFF-state current. The p-type pocket regions added to improve device performance in subthreshold region showing reduction in OFF-state leakage current leading to good value of ON/OFF current ratio as compared to other similar TFET structures. A high-value ION/IOFF ratio and good subthreshold behavior are observed for pocket JLTFET with 2 nm gate length and body thickness 0.5 nm. The proposed JLTFET is further optimized for different gate contact and oxide materials. The temperature analysis plays major role in deciding a reliable ON-state and OFF-state performance of transistors. So, the proposed pocket JLTFETis investigated for harsh temperature conditions to characterize the performance for DC and AC parameters. The sensitivity of proposed JLTFET is analyzed under different temperature conditions in range of (200–400) K to observe subthreshold performance such as transfer characteristics, Output characteristics and ION/IOFF ratio. The proposed designs for JLTFETs have been simulated using TCAD 2D/3D device simulator.

Design optimisation of junctionless TFET biosensor for high sensitivity

In this paper, a dielectric modulated junctionless TFET (DM-JLTFET) based structure is examined and proposed for the first time to inspect label free recognition of biological molecules like compound, cell, DNA, and so on. The variation in the threshold voltage and potential of the proposed structure has been utilised as the sensing parameter to distinguish the biological molecules. In the present literature, there is a presumption that the entire nanogap region is filled with biological molecules after confinement and hybridisation. A study is presented here to describe the impact of biological molecule’s fill in factor on the drain current characteristics of the proposed structure. The presence of biomolecules in a small area inside the cavity can lead to noticeable changes in the electrical properties of the device, resulting in high sensitivity. The proposed device structure gives noticeable results for both types of biological molecules (neutral and charged).

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

Metal-strip approach on junctionless TFET in the presence of positive charge

In this research, to achieve steep subthreshold slope, high $${I}_\mathrm{{on}}/{I}_\mathrm{{off}}$$ ratio and low ambipolarity in TFETs, we have proposed a device which consists of metal strips near drain–channel and source–channel interfaces. The proposed device is named as dual metal-strip charge plasma-based junction-less tunnel FET (DMS-CP-JL-TFET), which will improve the device performance in terms of DC and analog/RF figure of merits (FOMs). The introduction of a metal strip near the drain–channel interface which produces a wider energy gap reduces ambipolarity, while the metal strip near the source–channel interface delivers abruptness at the junction, leading to a better subthreshold slope and higher $${I}_\mathrm{{on}}/{I}_\mathrm{{off}}$$ ratio. Also, positive trap charge (PTC) is taken in the simulations, because the proposed devices have shown great improvement in the presence of PTC, which has also been discussed in this work. In supporting our work, we have added the optimization part for metal strips (M1 and M2) in terms of work functions, lengths to achieve better electrical characteristics.

Design and Investigation of the Junction-Less TFET with Ge/Si0.3Ge0.7/Si Heterojunction and Heterogeneous Gate Dielectric

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

Design and analysis of energy efficient semi-junctionless n+n+p heterojunction p-channel tunnel field effect transistor

This paper investigates the electrical characteristics of a novel p-channel InAs-GaAs0.1Sb0.9 Semi-Junctionless Tunnel Field Effect Transistor (SJTFET). Unlike the conventional TFET with p-i-n (n-i-p) doping profile, the proposed structure has similar doping density in the source and channel regions, which not only facilitates simpler fabrication process, but also enables scaling of the device without a power penalty. In addition, in comparison with junctionless TFET with additional gate contact over the source region, the proposed device provides a steep slope transfer characteristics with gates just over the channel region, which simplifies fabrication of the device. The workfunction difference between the metal gate and the channel modifies the hole density in the channel. The sensitivity of SJTFET, expressed in percentage, is defined as the ratio of the standard deviation to the mean value of electrical parameters with respect to the variation of design parameters. The results reveal that the gate workfunction, source-channel doping density and channel thickness are critical design parameters that may dramatically affect the device performance. In addition, for optimizing the performance of SJTEFT, the 2D variation matrix of off-state current is calculated as a function of challenging design parameters. The main feature of the proposed device is that the off-state current and threshold voltage are less sensitive to the variation of gate length and drain voltage, which boosts scaling of the device in nanoscale regime.

Label Free Detection of Biomolecules Using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET

Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.

Impact of asymmetric dual-k spacers on tunnel field effect transistors

In this paper, we propose a novel device structure for tunneling FETs, based on charge plasma concept, such as junctionless-TFET (JLTFET) and dopingless-TFET (DLTFET) with asymmetric dual-k spacer. Using 2-D simulations, we demonstrate that ON-state current increases significantly with the use of asymmetric dual-k spacers between the gate and p-gate/source in JLTFET and DLTFET. We optimize the spacer length ( $$L_\mathrm{S}$$ ) between gate and p-gate/source for these transistors having low-k spacer only. We have employed dual-k spacer, which consists of high-k spacer on gate side and low-k spacer on source side, which could also be interchangeably used. We also optimize the inner high-k spacer length for better analog and digital performance and investigate their impacts on the transistor performance. The simulation results for asymmetric dual-k spacers JLTFET (ADK-JLTFET) offer an improvement of two orders in ON-state current, with point subthreshold slope of 40 mV/dec, and a high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio of $$\sim 10^{8}$$ . We estimate the improvement in digital performance using ‘ $$I_{\mathrm{o}}/C_{\mathrm{in}}$$ ’ ( $$I_{\mathrm{D}}/C_{\mathrm{GG}}$$ ) and analog performance using unity gain frequency ‘ $$f_{\mathrm{T}}$$ ’ as the figure of merit. We observe that the proposed ADK-JLTFET offers 30 times increase in $$I_{\mathrm{o}}/C_{\mathrm{in}}$$ and 24 times increase in $$f_{\mathrm{T}}$$ as compared to JLTFET with only low-k spacer. Due to similar working mechanism, ADK-DLTFET also shows similar improvements.

Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement

This study investigates a junctionless tunnel field-effect transistor with a dual material gate and a heterostructure channel/source interface (DMG-H-JLTFET). We find that using the heterostructure interface improves device behavior by reducing the tunneling barrier width at the channel/source interface. Simultaneously, the dual material gate structure decreases ambipolar current by increasing the tunneling barrier width at the drain/channel interface. The performance of the device is analyzed based on the energy band diagram at on, off, and ambipolar states. Numerical simulations demonstrate improvements in ION, IOFF, ION/IOFF, subthreshold slope (SS), transconductance and cut-off frequency and suppressed ambipolar behavior. Next, the workfunction optimization of dual material gate is studied. It is found that if appropriate workfunctions are selected for tunnel and auxiliary gates, the JLTFET exhibits considerably improved performance. We then study the influence of Gaussian doping distribution at the drain and the channel on the ambipolar performance of the device and find that a Gaussian doping profile and a dual material gate structure remarkably reduce ambipolar current. Gaussian doped DMG-H-JLTFET, also exhibits enhanced IOFF, ION/IOFF, SS and a low threshold voltage without degrading IOFF.

Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics

In this work, we investigate for the first time dual material control gate junctionless tunnel-field effect transistor (DMCG-JLTFET) to improve the metrics in terms of DC, analog/RF parameters, and linearity performance. In this regard, we have considered N-type heavily doped silicon and formation of P+ source and intrinsic region beneath gate are performed by work-function engineering (dual material) concept with the deposition of metal electrodes over the silicon body, while, the drain region and the gap between source and channel remains with its original N+ doping. This forms the P+-N+-I-N+ gated structure similar to pocket doped TFET and prevents the device from random dopant fluctuations (RDFs). The gate electrode used to form the intrinsic region is partitioned into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with work-functions ϕM1, ϕM2 and ϕM3, respectively where (ϕM1 = ϕM3 < ϕM2). Appropriate work-functions for the gate electrodes (M1, M2 and M3) in DMCG-JLTFET are used to address the trade-off between the ambipolarity and RF/linearity parameters. It provides superior results in terms analog/RF and linearity performance as compared to other possible combinations.

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length (L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application

In this paper, a gate-all-around junctionless tunnel field effect transistor (JLTFET) based on heterostructure of compound and group III–V semiconductors is introduced and simulated. In order to blend the high tunneling efficiency of narrow band gap material JLTFETs and the high electron mobility of III–V JLTFETs, a type I heterostructure junctionless TFET adopting Ge–AlxGa1−xAs–Ge system has been optimized by numerical simulation in terms of aluminum (Al) composition. To improve device performance, we considered a nanowire structure, and it was illustrated that high-performance logic technology can be achieved by the proposed device. The optimal Al composition founded to be around 20 % (x = 0.2). The numerical simulation results demonstrate that the proposed device has low leakage current IOFF of ~1.9 × 10−17, ION of 4 µA/µm, ION/IOFF current ratio of 1.7 × 1011 and subthreshold swing SS of 12.6 mV/decade at the 40 nm gate length and temperature of 300 K.