Design and analysis of energy efficient semi-junctionless n+n+p heterojunction p-channel tunnel field effect transistor

Abstract

This paper investigates the electrical characteristics of a novel p-channel InAs-GaAs0.1Sb0.9 Semi-Junctionless Tunnel Field Effect Transistor (SJTFET). Unlike the conventional TFET with p-i-n (n-i-p) doping profile, the proposed structure has similar doping density in the source and channel regions, which not only facilitates simpler fabrication process, but also enables scaling of the device without a power penalty. In addition, in comparison with junctionless TFET with additional gate contact over the source region, the proposed device provides a steep slope transfer characteristics with gates just over the channel region, which simplifies fabrication of the device. The workfunction difference between the metal gate and the channel modifies the hole density in the channel. The sensitivity of SJTFET, expressed in percentage, is defined as the ratio of the standard deviation to the mean value of electrical parameters with respect to the variation of design parameters. The results reveal that the gate workfunction, source-channel doping density and channel thickness are critical design parameters that may dramatically affect the device performance. In addition, for optimizing the performance of SJTEFT, the 2D variation matrix of off-state current is calculated as a function of challenging design parameters. The main feature of the proposed device is that the off-state current and threshold voltage are less sensitive to the variation of gate length and drain voltage, which boosts scaling of the device in nanoscale regime.