Electrical performance of InAs/GaAs0.1Sb0.9 heterostructure junctionless TFET with dual-material gate and Gaussian-doped source

Abstract

In this work, we demonstrate the design of a dual-material gate and Gaussian-doped source heterostructure junctionless tunnel field-effect transistor (DMG-GDS-HJLTFET). Unlike the conventional dual-material gate heterostructure junctionless tunnel field-effect transistor (DMG-HJLTFET), the proposed structure uses a Gaussian-doped source and adopts InAs/GaAs0.1Sb0.9 as a heterojunction at the source and channel interface, where a polarization electric field is induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 Zinc blende crystal. At the same time, the control gate electrode of the proposed structure is divided into two parts, namely tunnel gate (TG) and auxiliary gate (AG). In this structure, TG is located near the source side and has a lower work function, while AG is located near the drain side and has a higher work function, which not only improves ON-state current (Ion) but also decreases the OFF-state current. The performance of the proposed device is analyzed and compared with that of DMG-HJLTFET; simulation results show improvements in Ion, subthreshold swing, transconductance (gm), cut-off frequency (fT) and gain bandwidth (GBW). Compared with conventional DMG-HJLTFET, the maximum Ion and gm of the DMG-GDS-HJLTFET are 4.1 × 10−4 A μm−1 and 1.27 × 10−3 S μm−1 at 1.2 V gate-to-source voltage (Vgs); further, average subthreshold swing of DMG-GDS-HJLTFET is only 13.6 mV Dec−1 at low drain voltages. Also, DMG-GDS-HJLTFET could obtain a maximum fT of 193 GHz at Vgs = 0.8 V and a maximum GBW of 55.7 GHz at Vgs = 1.12 V, respectively.