Junctionless MOSFET Research Articles

Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS Inverter With 3-nm Critical Feature Size Using Charge Sheet

In this paper, after calibrating the models and parameters used in the simulations based on experimental data, by using the opposite doping in the channel and between the gates in an asymmetric double-gate junctionless (JL) transistor with the 3nm gate length, a charge sheet (CS) was created. The results showed that, due to creating CS in the middle of the channel, the horizontal electric field was increased, thus more major carriers were depleted from the middle of the channel. With the analysis of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ DS}} - \text{V}_{\mathrm{ GS}}$ </tex-math></inline-formula> diagrams at different temperatures, it was concluded that in the CS JL MOSFET, while the ON-state current is very close to compared that in the JL MOSFET (same structure without CS), the drain leakage current has decreased by around 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . Furthermore, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ DS}} - \text{V}_{\mathrm{ DS}}$ </tex-math></inline-formula> diagram showed that the drain current in the CS JL MOSFET was much less affected by the drain voltage compared to that in the JL MOSFET. Also in AC analysis and at 1MHz frequency, by using CS the parasitic capacitances were reduced. Due to the improvement obtained in the presence of the charge sheet, the proposed structure was used in designing an inverter. The results showed that in the presence of the charge sheet, logical high input range, and logical low input range were increased, and also, noise margin low (NM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> ) and noise margin high (NM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> ) were improved.

Π-Shape Silicon Window for Controlling OFF-Current in Junctionless SOI MOSFET

In this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly. The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device.

Analytical Modelling of Symmetric Gate Underlap Quadruple Gate Multichannel Junctionless MOSFET Biosensor

Analytical Modelling of Symmetric Gate Underlap Quadruple Gate Multichannel Junctionless MOSFET Biosensor

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications

An analytical 2-D model of triple metal double gate graded channel junctionless MOSFET with hetero-dielectric gate oxide stack

In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO2 and HfO2 is derived. The model illustrates higher drive current and better performance against hazardous SCEs and HCEs in below 30 nm regime. Parabolic approximation method is used here to construct channel potentials and electric fields by solving 2-D Poisson's equation with applicable boundary conditions. The basic central and surface potentials as well as central and surface electric fields are being illustrated, Threshold voltage, DIBL, sub-threshold swing (SS) and a compact current model have also been deduced. These parameters clearly show the benefits of proposed graded-channel triple-metal double-gate structure with hetero-dielectric gate oxide stack. The device has reliability in low power applications because of its better Ion and Ioff control. Finally, the analytical model is validated with self-consistent numerical calculations to illustrate better performance of among available junctionless devices.

Structural and electrical characterisation of PtS from H2S-converted Pt

A manufacturing-compatible 300 mm chamber reactor for atomic layer deposition or chemical vapour deposition, and pre-fitted with H2/H2S gases that can be uniformly delivered to the wafer surface, is employed to thermally convert Pt to PtS in a H2/H2S gaseous atmosphere for 7 hours at a chamber temperature of 550 °C. Prior to conversion, platinum layers 5 nm thick are uniformly deposited by electron beam evaporation onto ∼30 nm of amorphous aluminium sesquioxide deposited by atomic layer deposition on, (a) p-type silicon, and (b) c-plane sapphire. Structural characterisation is performed by high-resolution cross-sectional transmission-electron microscopy, scanning-electron microscopy and Raman spectroscopy, confirming the formation of continuous films of polycrystalline platinum monosulfide (PtS) with a ∼15 nm thickness. Electrical characterisation is performed by 4-point resistivity and Hall-effect transport measurements on van der Pauw structures of PtS on aluminium sesquioxide on c-plane sapphire, and by back-gate junctionless MOSFET device measurements for PtS on aluminium sesquioxide on p-type silicon, showing that PtS behaves as a semiconductor with a mobility of ∼16 cm2/V.s and with an n-type carrier concentration of ∼1.2 × 1015 cm−3. Advanced commercial-grade Sentaurus simulations, alongside density-functional theory calculations, agree well with the experimental observations and suggest a large bandgap of ∼1.58 eV may be possible that could lead to a low off-current and a high Ion/Ioff ratio, suggesting that PtS may be an advanced material candidate for future device integration with CMOS and for 3D integration applications in Beyond-CMOS and More-than-Moore technologies.

Impact of Hot Carrier Aging on the 1/f and Random Telegraph Noise of Short-Channel Triple-Gate Junctionless MOSFETs

The low-frequency noise of short channel triple-gate junctionless (TG JL) MOSFET has been investigated in the frequency and time domains before and after hot carrier aging (HCA). The objective of this work is to investigate the interaction between HCA/flicker noise (1/f noise) and random telegraph noise (RTN) of short channel length device (L = 25 nm) exhibiting high density of interface traps. Significant variation in the noise spectral density has been observed between the fresh and the stressed device, related to the occurrence of generation-recombination (g-r) noise. Gate voltage dependence of g-r noise has been observed, assigned to gate dielectric traps and interface traps. In the fresh device, the noise is dominated by 1/f noise and multiple level RTN due to interface traps. In the stressed device, the 1/f noise is overlaid by multiple level RTN due to traps in the gate dielectric and at the gate insulator-silicon interface. The multiple level RTN relative amplitude can be described by the generic carrier number with correlated mobility fluctuations model as for the two level RTN detected in long channel devices (L = 65 and 95 nm).

Analytical Modeling and Simulation of Gate-All-Around Junctionless Mosfet for Biosensing Applications

Analytical Modeling and Simulation of Gate-All-Around Junctionless Mosfet for Biosensing Applications

2-D Analytical Modeling and Simulation of Dual Material, Double Gate, Gate Stack Engineered, Junctionless MOSFET based Biosensor with Enhanced Sensitivity

2-D Analytical Modeling and Simulation of Dual Material, Double Gate, Gate Stack Engineered, Junctionless MOSFET based Biosensor with Enhanced Sensitivity

Investigation of 4H-SiC gate-all-around cylindrical nanowire junctionless MOSFET including negative capacitance and quantum confinements

Investigation of 4H-SiC gate-all-around cylindrical nanowire junctionless MOSFET including negative capacitance and quantum confinements

Analytical Modeling and Performance Analysis of Surface Potential for Junctionless MOSFET

The advancement in semiconductor technology requires small devices with low power consumption. This paper presents an analytical modeling of surface potential for junctionless MOSFET. Parabolic approximation is utilized to find out the surface potential. The effect of device parameter variation on surface potential and electric field has been studied. The variation in gate work function has been investigated for surface potential. Moreover, the consequence of variations in device parameters like drain bias, gate length ratio, radius of silicon pillar and doping concentration are also inspected. It is found that present device shows an excellent behaviour for future VLSI chips. The analytical results are matched with the TCAD results which validates the model.

Performance evaluation of junctionless double surrounding gate In0.53Ga0.47As nanotube MOSFET using dual material gate engineering

In this paper, the authors present the studies made on drain current (ID) for 5 nm gate length Dual Material (DM) Double Surrounding Gate (DSG) inversion mode (IM) and junctionless (JL) In0.53Ga0.47As nanotube (NT) MOSFET and Silvaco ATLAS 3D TCAD based simulation results are reported. In these studies, the authors have made use of the Non-Equilibrium Green’s Function (NEGF) approach and the self-consistent solution of Poisson’s equation with Schrodinger’s equation. In the case of inversion mode nanotube MOSFET, the channel region is lightly doped. The effect of Dual Material Gate Engineering for In0.53Ga0.47As Nano Tube channel radius 1.5 nm with gate oxide (Al2O3) thickness (0.8 nm) on ID, has also been studied. Further, a comparison of results has been done between IM DM DSG and JL DM DSG NT MOSFET. In the case of JL MOSFET, doping concentrations are optimized for two approaches (i) to get the same ION current as IM device and (ii) to get the same threshold voltage (VTH) as IM device. This results in 10 and 102 times smaller IOFF in matching ION and VTH optimized devices respectively as compared to IM device. It was found that DM Gate Engineering reduces drain induced barrier lowering (DIBL) in IM and JL devices. JL device is found to have much smaller DIBL ~ 21.10 mV/V, almost an ideal SS ~ 60 mV/dec, and a higher ION/IOFF ratio ~ 2.85 × 108 as compared to the results available for CGAA devices in the literature.

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

This study investigated the position of electrons and holes in the ON and OFF states of double-gate junctionless transistors, and then three structures were proposed to create an electron-filled region exposing the drain-side inside the channel to the electron screening effect. Formation of an electron cloud in the channel and on the drain-side damps the electric field resulting from the drain voltage as the electric field passes through the electron cloud before reaching the main channel. Accordingly, in the structure with a drain-side gate, with the electric field decay introduced by the drain to the main channel, the carrier density increased compared to other structures, eventually reducing drain leakage current and improving the channel length modulation (CLM), threshold voltage, drain induced barrier lowering effect, and subthreshold slope in this structure. In the N+ pocket structure, despite the decrease in the electric field resulting from the drain voltage, the drain leakage current and the CLM were increased. In the N+ SiGe pocket structure, although the electric field resulting from the drain voltage along the channel length was reduced compared to the main structure, the drain leakage current and CLM experienced an increase. Moreover, the results showed that at low drain voltages, the drain leakage current in the N+ pocket structure was higher than that of the N+ SiGe pocket, but at high drain voltages, the order was reversed.

Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs

Quantum confinement effects tend to diminish gate control over the channel, further degrading the channel electrostatics of short channel Double-Gate (DG) Silicon-on-Insulator (SOI) MOSFETs. In this work, we first design an n-channel Junction-less (JL) DG MOSFET with a channel length (Lg) of 10 nm, where the source/drain doping, determined through Technology Computer-Aided Design (TCAD) simulations, enables better gate control for different channel thicknesses (tch) and oxide thicknesses (tox). The source/drain doping, thus determined, enables JL DG MOSFETs to overcome quantum confinement effects while also achieving key ITRS (International Technology Roadmap for Semiconductors) targets in terms of sub-threshold slope (S) and threshold voltage (Vth). We then introduce a heavily doped symmetric p-type silicon layer at the interface of the channel region with the top/bottom oxide such that the thickness and doping of the p-type layer enable tuning of the threshold voltage. In this partially JL DG MOSFET, by replacing the n-type doped silicon with n-type silicon–germanium (Si0.7Ge0.3) of lower doping, determined through TCAD simulations, we continue to demonstrate excellent channel electrostatics (ITRS targets) at short channel lengths (Lg = 10 nm) over a wide range of channel and oxide thicknesses while also showing enhanced strong inversion channel currents.

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

Work function optimization for enhancement of sensitivity of dual-material (DM), double-gate (DG), junctionless MOSFET-based biosensor

In this work, the impact of gate material work function on the sensitivity of dual-material, double-gate, junctionless MOSFET ( $$DMDG-JL-MOSFET$$ )-based biosensor has been studied. To enhance the sensitivity of the biosensor, optimization of gate work functions has been done through Sentaurus TCAD simulator. With the immobilization of biomolecules in the cavity at different value of work function of gate metal 1 (M1) and gate metal 2 (M2), i.e., WF1 and WF2, enhancement in sensing metrics (change in threshold voltage $$S_{V{\rm th}}$$ and $$I_{ON}$$ / $$I_{OFF}$$ ratio) is observed. The enhancement in sensitivity is profound in source-side gate (M1) work function (WF1) optimization as compared to drain-side gate (M2) work function (WF2) optimization. Sensitivity of 90 mV is observed in source-side gate work function optimization which is $$\sim$$ 89% more than the sensitivity of 23 mV which is achieved in drain-side gate work function optimization for a fixed concentration and dielectric constant of biomolecules. It has also been noted that the proposed structure exhibits $$\sim 90\%$$ higher sensitivity than the single-material, dual-gate, junctionless MOSFET ( $$SMDG-JL-MOSFET$$ ) biosensor. Results showcase that the optimization of gate metal work functions enhances the sensitivity of the biosensor.

Study and Analysis of Advanced 3D Multi-Gate Junctionless Transistors

As the IC technology is evolving very rapidly, the feature size of the device has been migrating to sub-nanometre regime for achieving the high packing density. To continue with further scaling of ICs, some novel devices such as multiple-gate silicon-on-insulator (SOI) devices, Gate-All-Around (GAA) nanowire and Nanotube MOSFETs have been proposed by researchers in recent years. The short channel transistor below 10 nm needs to have ultra-sharp junctions at source and drain ends with the channel region. The creation of such a sharp junction is quite challenging process from fabrication point of view. Therefore, junctionless transistors (JLT) were proposed to eradicate junction’s related issues, exhibit full CMOS functionality. The multigate junctionless transistors have been proposed, designed and fabricated. This paper illustrated basic working mechanism and behaviour of the various single and multi-gate junctionless MOSFETs. Junctionless nanowires transistor with single circular gate and gate material engineered techniques has also been explained. From simulation results, it has been observed that junctionless Nanotube GAA MOSFET has shown superior electrical behaviour over the Nanowire GAA MOSFET. Junctionless GaAs-Nanotube MOSFET has shown tremendous response over Junctionless Si-Nanotube MOSFET in terms of leakage and ON current. Junctionless GaAs-Nanotube MOSFET may be observed as alternate candidate for future CMOS applications.

Continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs

In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation of the terminal charges, verified against TCAD simulation data. The AC symmetry tests of the trans-capacitance compact model are thoroughly investigated.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub &amp; Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

Analytical Modeling of Surrounding Gate Junctionless MOSFET Using Finite Differentiation Method

In this paper, a novel two-dimensional analytical model for threshold voltage on Dual Material Surrounding Gate Junctionless MOSFET is proposed. The analytical study is aimed at decomposing the 2-D Poisson Equations into two 1-D equations. This decomposition enables modeling of Dual Material Gates into two individual single gates. For this prospect, the Finite Differentiation Method is applied. The decomposed individual 1-D Poisson models are combined by employing relevant boundary constraints. This, in turn, provides a normal and easy solution for equation related to complex 2-D Poisson. The proposed potential model facilitates expressions of threshold voltage and sub-threshold swing. Finally, the simulation results and the analytical results were compared with the simulations obtained from TCAD which showed significant compatibility. Thus, it is defended that the proposed model illustrates the guidance regarding the designing of Dual Material Surrounding Gate Junctionless MOSFETs.