Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs

Harshit Kansal,Aditya Sankar Medury

doi:10.1063/5.0038244

Harshit Kansal, Aditya Sankar Medury

Open Access

https://doi.org/10.1063/5.0038244

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Abstract

Quantum confinement effects tend to diminish gate control over the channel, further degrading the channel electrostatics of short channel Double-Gate (DG) Silicon-on-Insulator (SOI) MOSFETs. In this work, we first design an n-channel Junction-less (JL) DG MOSFET with a channel length (Lg) of 10 nm, where the source/drain doping, determined through Technology Computer-Aided Design (TCAD) simulations, enables better gate control for different channel thicknesses (tch) and oxide thicknesses (tox). The source/drain doping, thus determined, enables JL DG MOSFETs to overcome quantum confinement effects while also achieving key ITRS (International Technology Roadmap for Semiconductors) targets in terms of sub-threshold slope (S) and threshold voltage (Vth). We then introduce a heavily doped symmetric p-type silicon layer at the interface of the channel region with the top/bottom oxide such that the thickness and doping of the p-type layer enable tuning of the threshold voltage. In this partially JL DG MOSFET, by replacing the n-type doped silicon with n-type silicon–germanium (Si0.7Ge0.3) of lower doping, determined through TCAD simulations, we continue to demonstrate excellent channel electrostatics (ITRS targets) at short channel lengths (Lg = 10 nm) over a wide range of channel and oxide thicknesses while also showing enhanced strong inversion channel currents.

Highlights

The aggressive shrinking of MOSFETs, resulting in higher circuit speeds and greater integrated circuit density, has followed Dennard’s law of scaling1 and has propelled the semiconductor industry
Through Technology Computer-Aided Design (TCAD) simulations, we have first shown the adverse impact of quantum confinement effects on channel electrostatics, including the sub-threshold slope of conventional DG SOI MOSFETs
MOSFETs due to quantum confinement effects, we have considered the junction-less DG MOSFET as an alternate device architecture

Summary

Introduction

The aggressive shrinking of MOSFETs, resulting in higher circuit speeds and greater integrated circuit density, has followed Dennard’s law of scaling and has propelled the semiconductor industry. Among SOI MOSFETs, the symmetric Double-Gate (DG) SOI MOSFET, shown, both in its planar and non-planar forms (FinFET), has been a device of considerable interest due to good short-channel effect (SCE) immunity and better channel electrostatics, enabling greater channel length scaling.. Among SOI MOSFETs, the symmetric Double-Gate (DG) SOI MOSFET, shown, both in its planar and non-planar forms (FinFET), has been a device of considerable interest due to good short-channel effect (SCE) immunity and better channel electrostatics, enabling greater channel length scaling.3 This scaling of the channel length of symmetric DG SOI MOSFETs is made possible through the aggressive reduction in the SOI channel thickness and oxide thickness.. II, we outline the Technology Computer-Aided Design (TCAD) device simulation methodology followed to simulate the channel electrostatics of different DG MOSFET architectures being presented in this work

Results

Discussion

Conclusion