Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications

Abstract

Junctionless double gate (JLDG) MOSFET in sub nano meter regime has been the preferred choice for researchers as the leakage current in a JLDG MOSFET is significantly less compared to junction based double gate (DG) MOSFET. Also since the conduction mechanism in JLDG MOSFET is bulk conduction instead of surface channel conduction, the short channel effects (SCEs) get significantly reduced. In this research paper, major reliability issues concerning JLDG MOSFET has been studied and discussed. This research paper considers the gate misalignment effect and analysis of the thermal stability by subjecting the temperature variation from 200K to 500K. Gate misalignments is one of the major reliability issues and with enhancement in second order effects, it causes reduction in on current that degrades the performance of a JLDG MOSFET. The alignment between front and back gate critically influences the performance of a JLDG device. Misalignment effect in the device occurs due to shift in the back gate either towards the drain side or the source side. The gate misalignment therefore introduces some non-ideal effects from overlap or non-overlap regions. Thermal stability of the device has been tested for operating the device over a wide range of temperatures ranging from 200K to 500K, so that the effect of temperature on the performance issues remains limited. Further, the analog/RF performance parameters have been evaluated and linearity distortion analysis due to gate misalignment effect in terms of major performance matrices has been investigated. The investigated results show that there exist a thermally stable point in and around which if the device operates would be more stable.