Abstract
In this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly. The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device.
Highlights
The junctionless transistors are paid more attention nowadays because the fabrication of these devices is easier than conventional structures [1,2,3]
We have focused on the controlling off-current and thermal performance of the SOI Junctionless MOSFET (JMOSFET)
A new structure that is named as Silicon Region Junctionless MOSFET (SR-JMOSFET) is compared with Conventional Junctionless MOSFET (C-JMOSFET) with ATLAS simulation
Summary
The junctionless transistors are paid more attention nowadays because the fabrication of these devices is easier than conventional structures [1,2,3]. In the other words, creating junctions is difficult process in the fabrication and they are source of current leakage that waste power and heat [4]-[5] In such devices, the reverse bias voltage to the gate is not applied for the turning off them. Junctionless transistors are applied in the thin film silicon to have lower leakage current Using this technology in the acceptable silicon thickness makes considerable challenges for design and fabrication [7,8,9,10]. Low leakage current is result of reducing silicon layer of the active region. The goal of the new structure is using silicon window in the buried oxide The shape of this silicon layer is very important to have optimal electrical parameters.
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