Junctionless Double Gate MOSFET Research Articles

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

The purpose of this study is to investigate the possibilities of the junction-less double-gate (JLDG) MOSFET structure with gallium nitride (GaN) channel material to overcome the limitations of conventional MOSFET structures in improving device performance at scaled gate lengths and voltages. The design targets of this study are the doping profile (ND), and gate work function (Ф). The device has been modeled using the Silvaco Atlas 2D device simulator. The proposed model has been validated by calibrating it against the parabolic potential-based analytical model for short-channel JLDG MOSFETs in the subthreshold regime of Jazaeri et al. Device figure of merits (FOMs) such as ON-current (ION), ON-OFF current ratio (ION/IOFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) have been evaluated. The maximum on-current, (ION) = 0.9 mA/μm, has been achieved by tuning the channel doping concentration (ND) to 1 × 1019 cm−3. Tuning the gate work function, (Ф) also has a substantial effect on the behavior of the device. The lowest OFF-state current (IOFF) of 1.24 × 10−16 A/μm and power dissipation of 9.69 × 10−17 W/μm have been found for gate work-function (Ф) = 5.1 eV (Au). In addition, the on-current to off-current ratio (ION/IOFF) of 7.56 × 1012 revolutionizes the applicability of the device in the semiconductor industry. Thus, the remarkable improvements in device FOMs prove that GaN-based JLDG MOSFETs are a strong contender for applications requiring low-power logic switching in the next generation.

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

Analytical Model of Subthreshold Swing for Junctionless Double Gate MOSFET Using Ferroelectric Negative Capacitance Effect

An analytical Subthreshold Swing (SS) model is presented to observe the change in the SS when a stacked SiO2-metal-ferroelectric structure is used as the oxide film of a JunctionLess Double Gate (JLDG) MOSFET. The SS of 60 mV/dec or less is essential to reduce power dissipation while maintaining transistor performance. If a ferroelectric material with Negative Capacitance (NC) effect is used, the SS can be reduced below 60 mV/dec. The analytical SS model of the ferroelectric NC FET presented to analyze this was in good agreement with the SS derived from the relation between the drain current and gate voltage, using 2D potential distribution. As results were derived from the analytical SS model, it was found that it is possible to obtain an SS of 60 mV/dec or less even at 15 nm channel length by adjusting the thicknesses of the silicon channel, SiO2, and ferroelectric. In particular, the change in SS according to the ferroelectric thickness was saturated as the thickness of SiO2 increased and was almost constant as the thickness of the silicon channel decreased. ABSTRAK: Model Ayunan Subambang (SS) analitikal dibentangkan bagi melihat perubahan pada SS apabila struktur feroelektrik-logam-SiO2 bertindan digunakan sebagai filem oksida bagi MOSFET Dua Get Tanpa Simpang (JLDG). SS 60 mV/dec atau kurang adalah penting bagi mengurangkan pelesapan kuasa sambil mengekalkan prestasi transistor. Jika bahan feroelektrik dengan kesan Kapasitans Negatif (NC) digunakan, SS dapat dikurangkan bawah 60 mV/dek. Model SS analitikal feroelektrik NC FET yang digunakan bagi kajian ini adalah sesuai dengan SS yang diperoleh daripada hubungan antara arus serapan dan voltan get, menggunakan edaran potensi 2D. Dapatan terbitan melalui model SS analitikal, mendapati bahawa adalah mungkin bagi mendapatkan SS pada 60 mV/dek atau kurang walaupun panjang laluan adalah 15 nm dengan melaraskan ketebalan saluran silikon, SiO2, dan feroelektrik. Terutama apabila perubahan ketebalan feroelektrik SS adalah tepu ketika ketebalan SiO2 meningkat, dan hampir malar apabila ketebalan saluran silikon berkurang.

Improvement in the Performance of III-V Channel Based Ultra-Thin Junction-Less-Hybrid CMOS Circuits with Mixed Mode Analysis

The logic performance of a hybrid complementary-metal-oxide-semiconductor (CMOS) circuit based on a novel technology known as a junctionless transistor constructed with high-K and III-V compound material Junction-Less-Double-Gate MOSFET (JL-DG-MOSFET) for ultra-low power applications is analyzed in this manuscript. The mentioned CMOS circuit is constructed by using a Ge-based P-MOS and GaAs-based N-MOS to analyze different performance metrics of inverter such as noise margin (NM), voltage transfer characteristics, transient response, gain, frequency response, and propagation delay using Mixed Mode Analysis. The aforementioned characteristics of the proposed inverter are analyzed and compared with the Si-based CMOS inverter and we observed that the proposed structure shows an improved circuit performance over the Si-based CMOS circuit. Consequently, the work is also extended to the design and performance of universal logic gates. The aforementioned N-MOS structure has a higher drive current of 1.3 mA, gm of 5.9 mS, gd of 20.8 mS, SS of 64 mV Decade−1, and DIBL of 23 mV V−1, whereas the Ge based P-MOS structure yields drive current of 0.7 mA, gm of 1.5 mS, gd of 5.6 mS, SS of 95 mV Decade−1, and DIBL of 21 mV V−1. The hybrid C-MOS structure has higher unity-gain bandwidth of 1100 GHz and lower propagation delay of 3.1 ps, as well as static and dynamic power dissipation of 1.86 nw and 0.23 mw.

Analytical Model of Dopingless Asymmetrical Junctionless Double Gate MOSFET

Analytical Model of Dopingless Asymmetrical Junctionless Double Gate MOSFET

Dual P+-Wire Double-Gate Junctionless MOSFET with 10-nm Regime for Low Power Applications

Dual P+-Wire Double-Gate Junctionless MOSFET with 10-nm Regime for Low Power Applications

Analysis of Subthreshold Swing of Symmetric Junctionless Double Gate MOSFET Using Gaussian Doping Profile

—The variation of subthreshold swing(SS) according to the projected range (Rp ) and standard projected deviation (σp ) was analyzed when the symmetrical junctionless double gate (JLDG) MOSFET was doped with Gaussian doping profile. For this purpose, the analytical SS model was presented. We compared with the TCAD results to turn out the validity of this model, and the SSs of this model agreed with those of TCAD. The effective conduction path and mean doping concentration affecting the SS were analyzed according to the Rp and σp . As a result, the SS increased as the Rp and σp increased simultaneously. The smaller the Rp and the larger the σp , the lower the SS. When Rp = 1.5 nm, it showed the SS below 100mV/dec without being affected by the change of σp or silicon thickness. When σp = 3nm, it was also 100mV/dec or less regardless of the change of Rp and silicon thickness. Keywords— Double gate, Junctionless, Subthreshold swing, Gaussian, Projected range, Standard projected deviation

Analysis of drain induced barrier lowering for junctionless double gate MOSFET using ferroelectric negative capacitance effect

<abstract> <p>We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It has been found that the results of this analytical DIBL model are very similar to those of the second derivative method. The results of this analytical DIBL model are also in good agreement with the results of TCAD. As a result, it was found that the negative DIBL phenomenon is caused by the change according to the drain voltage of the charge existing in the ferroelectric material. The negative DIBL phenomenon easily occurred as the ferroelectric thickness increased and the thickness of SiO<sub>2</sub> used as an insulator decreases.</p> </abstract>

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device’s response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm channel length have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

Improvements in FOMs and Thermal Effects of a III-V Compound Material Based Short-Channel Thin Film Junctionless Double Gate MOSFETs

Better figure of merits (FOMs) have been achieved by using III-V compound material based junctionless double gate metal-oxide semiconductor field-effect transistors (JL DG-MOSFETs), and a thorough analysis of the device’s performance over temperature has been performed using a highly N-doped GaAs-based JL DG-MOSFET using III-V compound material GaSb. GaSb, a compound material, is employed as the source material, which is well known for its greater mobility and injection velocity property with GaAs as the channel and drain materials, to obtain more output current and less leakage current due to the development of hetero structure (GaSb-GaAs) at the source-channel interface. The dielectric material HfO2 with a high k value is utilized to reduce the gate tunneling effects of electrons and enhance the control of the gate at the 20 nm channel length. Primary and auxiliary gates are taken to include ipact ionization on drain side for reducing the Subthreshold-swing. Numerous characteristics of a DG JLMOSFET, such as Id, SS, gm, TGF, Ion/Ioff, Cgs, and fT, GFP, TFP, GTFP are explored and compared with a silicon based material. The proposed structure shows an improved results comparing to the earlier model with Id of 117 mA, SS of 15.08 mV decade−1, gm of 0.62 A V−1, TGF of 38.8 V−1, Ion/Ioff ratio of 1.89 × 10 13, Cgs of 5.86 × 10 −16 F, fT of 2.05 × 10 15 Hz, GTFP of 1.81 × 10 17 Hz/V for the improvement of FOM in RF and DC analysis.

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x \({10}^{-6 }\)A/µm with reduced OFF-state leakage current up to1.37 x \({10}^{-17 }\)A/µm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 and 400 K shows a small variation in OFF-state current (< 15 %). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All design and analysis have been done with a 2D/3D Visual TCAD device simulator.

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

&lt;span&gt;The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO&lt;sub&gt;2&lt;/sub&gt;/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. &lt;/span&gt;&lt;span&gt;The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 10&lt;sup&gt;4&lt;/sup&gt; or less is shown for SiO&lt;sub&gt;2&lt;/sub&gt;, but the on-off current ratio for TiO&lt;sub&gt;2&lt;/sub&gt; (&lt;em&gt;k&lt;/em&gt;=80) increases to 10&lt;sup&gt;7&lt;/sup&gt; or more.&lt;/span&gt;

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

This study investigated the position of electrons and holes in the ON and OFF states of double-gate junctionless transistors, and then three structures were proposed to create an electron-filled region exposing the drain-side inside the channel to the electron screening effect. Formation of an electron cloud in the channel and on the drain-side damps the electric field resulting from the drain voltage as the electric field passes through the electron cloud before reaching the main channel. Accordingly, in the structure with a drain-side gate, with the electric field decay introduced by the drain to the main channel, the carrier density increased compared to other structures, eventually reducing drain leakage current and improving the channel length modulation (CLM), threshold voltage, drain induced barrier lowering effect, and subthreshold slope in this structure. In the N+ pocket structure, despite the decrease in the electric field resulting from the drain voltage, the drain leakage current and the CLM were increased. In the N+ SiGe pocket structure, although the electric field resulting from the drain voltage along the channel length was reduced compared to the main structure, the drain leakage current and CLM experienced an increase. Moreover, the results showed that at low drain voltages, the drain leakage current in the N+ pocket structure was higher than that of the N+ SiGe pocket, but at high drain voltages, the order was reversed.

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL =25.15ηL_g^(-3) t_si^2 √(t_ox1∙t_ox2 ), where η is a static feedback coefficients between 0 and 1. The η is found to be between 0.5 and 1.0 in this model. The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.

Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs

Quantum confinement effects tend to diminish gate control over the channel, further degrading the channel electrostatics of short channel Double-Gate (DG) Silicon-on-Insulator (SOI) MOSFETs. In this work, we first design an n-channel Junction-less (JL) DG MOSFET with a channel length (Lg) of 10 nm, where the source/drain doping, determined through Technology Computer-Aided Design (TCAD) simulations, enables better gate control for different channel thicknesses (tch) and oxide thicknesses (tox). The source/drain doping, thus determined, enables JL DG MOSFETs to overcome quantum confinement effects while also achieving key ITRS (International Technology Roadmap for Semiconductors) targets in terms of sub-threshold slope (S) and threshold voltage (Vth). We then introduce a heavily doped symmetric p-type silicon layer at the interface of the channel region with the top/bottom oxide such that the thickness and doping of the p-type layer enable tuning of the threshold voltage. In this partially JL DG MOSFET, by replacing the n-type doped silicon with n-type silicon–germanium (Si0.7Ge0.3) of lower doping, determined through TCAD simulations, we continue to demonstrate excellent channel electrostatics (ITRS targets) at short channel lengths (Lg = 10 nm) over a wide range of channel and oxide thicknesses while also showing enhanced strong inversion channel currents.

Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application

In this paper Junctionless Double Gate MOSFET based Efficient Charge Recovery Logic (JL-ECRL) circuits have been driven in sub-threshold regime for the first time in literature to implement the ultra low power systems where the performance is not pivotal issue. Analytical modeling of the power dissipation, delay and the power delay product (PDP) of the sub-threshold JL-Inverter structure have been detailed out. Impact of supply voltage, temperature and the variation of the process parameters like oxide thickness, silicon thickness, doping concentrations have been discussed in depth. Extensive simulations have been done using SILVACO ATLAS to validate analytical data of the power, delay and PDP of the proposed model for different channel length. Based on the analytical and simulated data, optimum conditions have been chosen for the proposed model. It has been observed that the proposed model can perform efficaciously in sub threshold regime without sacrificing noise immunity.

A nonlinear feed‐forward memory‐less model to fast prediction of threshold voltage in junction‐less double‐gate MOSFETs

AbstractDecreasing Drain‐Induced‐Barrier‐Lowering (DIBL) is one of the nondesirable short‐channel effects, causes the threshold voltage of the transistor to be reduced by increasing the drain voltage. DIBL makes it impossible for engineers to consider VT as a constant, and it is necessary to calculate VT as a function of the drain voltage. Therefore, to consider the DIBL effect in the design of ICs, a large computational burden is imposed on the system, which slows down the simulation process in circuit‐level simulators. Accordingly, a Nonlinear Feed‐Forward Memory‐Less (NFFML) model using the Gram‐Schmidt orthogonalization approach is proposed, which calculates the VT of the new generation of MOSFETs, that is, Junctionless Double‐Gate MOSFETs (JL‐DG‐MOSFETs), with high precision and a significant speed‐up in the computation of the model. It is shown that the proposed numerical method is 313 times faster than the state‐of‐the‐art analytical model. The normalized MSE is 0.435% on average, showing that the proposed approach can be a fast and accurate candidate for replacing the analytical modeling.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub &amp; Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

Analysis of gate engineered asymmetric junctionless double gate MOSFET for varying operating conditions

In this paperan asymmetrical junctionless double-gate MOSFET(AJDG-MOSFET) has been analyzed using different gate oxide material like SiO2 and HfO2 and different gate contact material like aluminium, copper and polysilicon. To check the sensitivity of AJDG-MOSFET, a temperature analysis has been performed at a different temperature ranging 250-400K. The performance of AJDG-MOSFET is analyzed with transfer and output characteristics using 2D/3D simulation on Cogenda TCAD. The device performs better using HfO2 as gate oxide and polysilicon as gate contact. The ideal subthreshold performance (DIBL=65mV/V, SS=68 mV/decade) is observed with a high value of Ion/Ioff(∼1012) for 300K temperature. The analysis for temperature shows a very small variation in OFF current and found suitable for low power applications.