GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

Abstract

The purpose of this study is to investigate the possibilities of the junction-less double-gate (JLDG) MOSFET structure with gallium nitride (GaN) channel material to overcome the limitations of conventional MOSFET structures in improving device performance at scaled gate lengths and voltages. The design targets of this study are the doping profile (ND), and gate work function (Ф). The device has been modeled using the Silvaco Atlas 2D device simulator. The proposed model has been validated by calibrating it against the parabolic potential-based analytical model for short-channel JLDG MOSFETs in the subthreshold regime of Jazaeri et al.. Device figure-of-merits (FOMs) such as ON-current (ION), ON-OFF current ratio (ION/IOFF), subthreshold slope (SS), and drain-induced barrier lowering (DIBL) have been evaluated. The maximum on-current, (ION) = 0.9 mA/μm, has been achieved by tuning the channel doping concentration (ND) to 1×1019 cm-3. Tuning the gate work function, (Ф) also has a substantial effect on the behavior of the device. The lowest OFF-state current (IOFF) of 1.24×10-16 A/μm and power dissipation of 9.69×10-17 W/μm have been found for gate work-function (Ф) = 5.1 eV (Au). In addition, the on-current to off-current ratio (ION/IOFF) of 7.56×1012 revolutionizes the applicability of the device in the semiconductor industry. Thus, the remarkable improvements in device FOMs prove that GaN-based JLDG MOSFETs are a strong contender for applications requiring low-power logic switching in the next generation.