Improvement in the Performance of III-V Channel Based Ultra-Thin Junction-Less-Hybrid CMOS Circuits with Mixed Mode Analysis

Abstract

The logic performance of a hybrid complementary-metal-oxide-semiconductor (CMOS) circuit based on a novel technology known as a junctionless transistor constructed with high-K and III-V compound material Junction-Less-Double-Gate MOSFET (JL-DG-MOSFET) for ultra-low power applications is analyzed in this manuscript. The mentioned CMOS circuit is constructed by using a Ge-based P-MOS and GaAs-based N-MOS to analyze different performance metrics of inverter such as noise margin (NM), voltage transfer characteristics, transient response, gain, frequency response, and propagation delay using Mixed Mode Analysis. The aforementioned characteristics of the proposed inverter are analyzed and compared with the Si-based CMOS inverter and we observed that the proposed structure shows an improved circuit performance over the Si-based CMOS circuit. Consequently, the work is also extended to the design and performance of universal logic gates. The aforementioned N-MOS structure has a higher drive current of 1.3 mA, gm of 5.9 mS, gd of 20.8 mS, SS of 64 mV Decade−1, and DIBL of 23 mV V−1, whereas the Ge based P-MOS structure yields drive current of 0.7 mA, gm of 1.5 mS, gd of 5.6 mS, SS of 95 mV Decade−1, and DIBL of 21 mV V−1. The hybrid C-MOS structure has higher unity-gain bandwidth of 1100 GHz and lower propagation delay of 3.1 ps, as well as static and dynamic power dissipation of 1.86 nw and 0.23 mw.