Energy losses and DVFS effectiveness vs technology scaling

Abstract

Purpose – This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS). Design/methodology/approach – Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology. Findings – Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption. Originality/value – This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.