Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application

Abstract

In this paper Junctionless Double Gate MOSFET based Efficient Charge Recovery Logic (JL-ECRL) circuits have been driven in sub-threshold regime for the first time in literature to implement the ultra low power systems where the performance is not pivotal issue. Analytical modeling of the power dissipation, delay and the power delay product (PDP) of the sub-threshold JL-Inverter structure have been detailed out. Impact of supply voltage, temperature and the variation of the process parameters like oxide thickness, silicon thickness, doping concentrations have been discussed in depth. Extensive simulations have been done using SILVACO ATLAS to validate analytical data of the power, delay and PDP of the proposed model for different channel length. Based on the analytical and simulated data, optimum conditions have been chosen for the proposed model. It has been observed that the proposed model can perform efficaciously in sub threshold regime without sacrificing noise immunity.