Interface Trap Research Articles

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

This work offers a comprehensive analysis of the adverse impact of interface trap charge (ITC) under the influence of temperature variation on a heterostacked (HS) source L-gate tunnel field effect transistor (TFET) having a SiGe pocket. An investigation of both static and radiofrequency (RF) characteristics has been carried out. It appears that ITCs situated at the Si–oxide interface fluctuate the flat-band voltage to alter the various analog/RF parameter characteristics. Uniform ITCs are seen to be less susceptible to degradation in device characteristics. Low-frequency noise (LFN) analysis has also been carried out considering the impact of different trap distributions (uniform and Gaussian) and densities, which are compared. The temperature dependence of LFN has been studied under the influence of different distributed ITCs, and this has rarely been explored. Moreover, a comparative analysis has been made of the device behavior and LFN characteristics of HS L-gate TFET structures with and without a SiGe pocket. Structures with SiGe pockets were found not to be susceptible to noise effects.

Impact of Interface Trap Charges on Silicon Carbide (4H-SiC) Based Gate – Stack, Dual Metal, Surrounding Gate, FET (4H-SiC- GSDM-SGFET) for Analog and Noise Performance Analysis for 5 G/LTE Applications

This article examines the impact of various interface trap charges on silicon carbide-based gate—stack, dual metal, surrounding gate, FET (4H-SiC-GSDM-SGFET). It has been contrasted for performance with silicon carbide (4H-SiC)-based dual metal, surrounding gate, FET (4H-SiC-DM- SGFET). For both devices, output characteristics including transconductance (gm), output conductance (gd), drain current (Ids), gate capacitance (Cgg), cutoff frequency (fT) and threshold voltage (Vth) have been examined. Surface potential and electron concentration were also inspected using a contour plot for both the device structures. A gate-stack with a high k- dielectric, Lanthanum oxide (La2O3) along with gate dielectric layer Aluminum oxide (Al2O3) was used for proposed structure implementation. Additionally, we investigated how trap charges affect noise figure (NF) and noise conductance (NC). Also, a CMOS inverter has been developed and its output characteristics have been compared for both the device architectures. ATLAS 3-D device simulator has been employed to conduct the simulations.

Noise analysis of NC-GAAFET cylindrical nanowire with non-uniform interface trap charge

In this article, low to high frequency noise behavior analysis of negative capacitance gate-all-around field effect transistor (NC-GAAFET) MFIS structure Silicon Nanowire (SiNW) device, using Sentauras TCAD simulations, is investigated. The NC-GAAFET SiNW yields on current (ION) 5.31 times larger and off current (IOFF) is significantly reduced by ∼ 105 orders compared to baseline SiNW. The device exhibits an excellent switching ratio of 5.2 × 1014. Average subthreshold swing for the NC-GAAFET is 33 mV/dec compared to 64 mV/dec of baseline nanowire. The Negative-DIBL for the device is −20 mV/V which outshines earlier findings. Furthermore, the drain current noise power spectral density (PSD) Sid, and input referred gate voltage noise PSD (Svg) are comprehensively analyzed in the presence of Gaussian trap (non-uniform) distribution. The analysis indicates that, flicker or (1/f) noise dominates in low frequency regime, generation-recombination (G-R) noise is more influential in mid frequency regime whereas in very high frequency regime diffusion noise is leading. The device exhibits least Sid(NET) and Svg(NET) at tfe = 6 nm compared to baseline, tfe = 5 nm, and 7 nm.

Temperature analysis of lead zirconate titanate GAA-NCFET nanowire with interface trap charges

This article explores the static and trap analysis of lead zirconate titanate negative capacitance gate-all-around (PZT NC GAAFET) nanowire at different temperature using Sentaurus 3D TCAD simulations. Impact of uniform and non-uniform trap charges on various electrical parameters for different ferroelectric (FE) layer thickness is investigated. Work delves the effect of interface traps, at Silicon-HfO2 interface, on electrical parameters of PZT NC GAAFET. Device yields subthreshold slope of 49 mV/dec, at TFE 20 nm, which surpasses Boltzmann tyranny limit. ION, IOFF, ION/IOFF, VTH, SS, and gm have enhanced owing to incorporation of PZT FE layer in contrast to baseline GAAFET. IDS-VGS of NC GAAFET evinces a positive (negative) shift for negative (positive) traps, owing to negative capacitance, compared to baseline for which it exhibits reverse shift. Moreover, the influence of interface trap charges, for NC GAAFET, prevails in subthreshold regime. Electrical parameters primarily deteriorate in presence of interface traps as temperature elevates.

64‐1: Protrusion‐free LTPS Using the CMP Process and Its OLED Application

Low Temperature Polysilicon (LTPS) is the most popular channel material used in the thin film transistor and it has the protrusions due to the volume expansion of Si and the presence of its native oxide. The protrusions cause the negative effects such as interface trap, hysteresis and so on. In that sense, the heights need to be lowered or eventually flattened.In this study, we used the chemical mechanical planarization (CMP) technique to reduce the surface roughness of LTPS to the 1nm and even lower. One of the most difficult problmes in the large sized CMP process is the removal of slurry residues after CMP and we successfully overcome the issue by using the hydrophilic angent.Finally, we are succesfully able to prepare AMOLED panel with reduced gate insulator thickness by using the CMP process and it shows less hysteresis results.

High performance Bi–Co–Mn–Si–B-doped ZnO varistors with wide ranging breakdown voltage and high resistance to electrical degradation

A simple ZnO varistor with high resistance to electrical degradation and an adjustable breakdown voltage range of 100–3000 V/mm was developed by adding SiO2 and B2O3 to Bi–Mn–Co-doped ZnO. Samples were fabricated by sintering at 1150 ºC and doped with 0–55 mol% SiO2 to adjust breakdown voltage. High nonlinear index and low leakage current density were confirmed with addition of SiO2; however, severe electrical degradation occurred. Addition of 1 mol% B2O3 successfully improved the resistance to electrical degradation and long-term reliability, due to the formation of homogenous glass-phase Bi–B–O at grain boundaries inhibiting ion migration. A stabilized interface trap with ∼0.6 eV and 10−21 (m2) was found in samples with 1 mol% B2O3.

Correlation of Radiation-Induced Interface Traps With Band Edge Energy Through Band Structure-Based Analysis of Electrostatics of UTB SOI Devices

Correlation of Radiation-Induced Interface Traps With Band Edge Energy Through Band Structure-Based Analysis of Electrostatics of UTB SOI Devices

Floating gate potential of gate-all-around floating gate memory cell: parameter extraction and compact model

The compact modeling of flash memories is crucial for integrated circuit designers to carry out efficient and precise circuit-level evaluations, particularly in the case of 3D NAND flash where the 3D geometry leads to significant parasitic coupling impacts on performance. In this work, we proposed a charge-based modeling approach for gate-all-around floating gate memory cells. The compact model is based on the derived unified charge control model where the mobile charge is explicitly solved. By solving the charge balance model and taking into account voltage-dependent parasitic capacitances for accurate coupling effects, the floating gate potential is accurately computed. The simulation results are validated with numerical TCAD simulation and showed good agreement with TCAD simulation. By solving the charge balance model and considering voltage-dependent parasitic capacitances for more accurate coupling effects, the floating gate potential is accurately calculated. Additionally, the results indicate that subthreshold degradation is caused by interface trap charge in the experimental device, and the proposed model successfully replicates experimental data.

Programmable Optoelectronic Synaptic Transistors Based on MoS2/Ta2NiS5 Heterojunction for Energy-Efficient Neuromorphic Optical Operation.

The optoelectronic synaptic transistors with various functions, broad spectral perception, and low power consumption are an urgent need for the development of advanced optical neural network systems. However, it remains a great challenge to realize the functional diversification of the systems on a single device. 2D van der Waals (vdW) materials can combine unique properties by stacking with each other to form heterojunctions, which may provide a strategy for solving this problem. Herein, an all-2D vdW heterojunction-based programmable optoelectronic synaptic transistor based on MoS2/Ta2NiS5 heterojunctions is demonstrated. The device implements reconfigurable, multilevel non-volatile memory (NVM) states through sequential modulation of multiple optical and electrical stimuli to achieve broadband (532-808nm), energy-efficient (17.2 fJ), hetero-synaptic functionality in a bionic manner. The intrinsic working mechanisms of the photogating effect caused by band alignment and the interfacial trapping defect modulation induced by gate voltage are revealed by Kelvin-probe force microscopy (KPFM) measurements and carrier transport analysis. Overall, the (opto)electronic synaptic weight controllability for combined in-sensor and in-memory logic processors is realized by the heterojunction properties. The proposed findings facilitate the technical realization of generic all 2D hetero-synapses for future artificial vision systems, opto-logical systems, and Internet of Things (IoT) entities.

Analysis of interface trap induced ledge in β-Ga2O3 based MOS structures using UV-assisted capacitance–voltage measurements

A ledge feature in the capacitance–voltage (CV) profiles of Ga2O3 MOS (metal–oxide–semiconductor) capacitors is investigated using UV-assisted CV measurements. A model is presented whereby the capacitance ledge is associated with carrier trapping in deep-level states at the Al2O3/Ga2O3 interface. Following UV assisted emptying of interface traps at a constant bias, a voltage ramp toward flatband results in a CV ledge when the trap recombination current becomes equal to the quasi-static sweep charging current. The ledge continues until all the traps below the corresponding pinned surface potential have been filled. Varying the UV energy varies the ledge voltage range and allows a density of states to be determined as a function of energy. A broad interface state peak with maximum density ∼8 × 1012 cm−2 eV−1 for deep trap energies lying between 2.4 and 4.1 eV below the conduction band (CB) edge is extracted. Using the conductance method, the interface trap density is also found to rise toward the CB edge in the range 0.25–0.45 eV below the CB edge, reaching a maximum density of ∼1 × 1012 cm−2 eV−1. Combining these two techniques, an interface trap distribution is estimated for almost the entirety of the bandgap of Ga2O3. This novel technique probes deep interface states where standard methods fail to quantify interface states reliably.

Revealing the high-performance of a novel Ge-Sn-Based perovskite solar cell by employing SCAPS-1D

In this study, a novel Ge-Sn based perovskite solar cell (PSC) with the structure FTO/WS2/ FA0.75MA0.25Sn0.95Ge0.05I3/MoO3/Ag has been designed and thoroughly analyzed employing SCAPS-1D. Drawing attention from the work of Ito et al where a similar perovskite-based PSC displayed a poor performance of ∼ 4.48% PCE, in which a large conduction band offset (CBO) acts as a critical factor contributing to interfacial recombination and device deterioration. To address this issue, we presented WS2 as an electron transport layer (ETL) along with MoO3 as a hole transport layer (HTL), both possessing compatible CBO and valence band offset (VBO) with perovskite material. Through systematic simulations and optimizations, remarkable improvements in the PSC’s performance have been acquired, getting a power conversion efficiency (PCE) of 18.97%. The optimized structure involved a 50 nm MoO3 HTL, 350 nm FA0.75MA0.25Sn0.95Ge0.05I3 light-harvesting layer (LHL), and a 50 nm WS2 ETL. Bulk defect densities for the LHL and ETL were optimized to 1 × 1015 cm−3 and 1 × 1018 cm−3, respectively, significantly superior values than that of reported value in the literature. Particularly, the tolerable defect density of ETL has increased 1000 times more than the published literature. The interfacial tolerable trap density for MoO3/perovskite increased from 1 × 1014 cm−2 to 1 × 1016 cm−2. The study also explored the impact of defects on quantum efficiency, revealing a severe negative influence beyond a perovskite bulk defect density of 1 × 1017 cm−3. Light intensity analysis demonstrated a correlation between incident light reduction and device performance decay. Capacitance–Voltage (C-V) and Mott–Schottky (M-S) have been analyzed during the study. Finally, the total recombination of the optimized device concerning thickness has been analyzed along with the dark J-V characteristics. The comprehensive insights gained from this work are anticipated to accelerate the fabrication of mixed Ge-Sn based PSCs with improved efficiency, paving the way for commercialization in the photovoltaic industry.

Achieving Near‐Ideal Subthreshold Swing in P‐Type WSe2 Field‐Effect Transistors

AbstractThe pursuit of near‐ideal subthreshold swing (SS) ≈ 60 mV dec−1 is a primary driving force to realize the power‐efficient field‐effect transistors (FETs). This challenge is particularly pronounced in 2D material‐based FETs, where the presence of a large interface trap density (Dit) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre‐patterned van der Waals (vdW)‐contacted p‐FETs, varying the WSe2 channel thickness from monolayer to ten‐layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing Dit. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SSmin) close to the thermal limit (≈60 mV dec−1), with a corresponding Dit of ≈1010 cm−2 eV−1, comparable to Dit values observed in state‐of‐the‐art Si transistors, when utilizing WSe2 channel thicknesses ≥ five‐layer. However, reducing the WSe2 channel thickness below the trilayer, SSmin (≈91 mV dec−1) deviates from the thermal limit, attributed to a comparatively higher Dit (≈1011 cm−2 eV−1), despite the still lower than values reported for surface‐contacted 2D transistors. Furthermore, all devices exhibit consistent p‐type characteristics, featuring a high ION/IOFF ratio, high mobility, and excellent electrical stability confirmed over several months.

Atom-Scaled Hafnium Doping for Strengthening the Germanium Oxide Interfacial Layer of The Gate Stack of Germanium P-Type Metal-Oxide-Semiconductor Field Effect Transistor

We have developed a method that uses a half-cycle Hf precursor adsorption to subtly dope GeO2 IL of the Hf-based gate stack through in situ plasma-enhanced atomic layer deposition. This technique can effectively reduce GeO vaporization and improve the thermal stability of the GeO2 layer. Our results indicated that the accumulation capacitance (Cacc) undergoing higher temperatures showed no noticeable increase in the capacitance-voltage (CV) curves once Hf was delicately introduced into the GeO2 layer. According to the Ge 3d spectra of X-ray photoelectron spectroscopy, we found that the IL had a signal from extra Hf-O bonds; thus, we conclude GeO evaporation can be suppressed substantially by Hf incorporation. As a result, adding metal into GeOx IL to form HfGeOx achieved a remarkably low leakage current of 9 × 10−5 A cm−2 and the lowest interface trap density (Dit) of approximately 2 × 1011 eV−1 cm−2 at 500 °C of PMA. In addition, applying this gate stack structure to device fabrication significantly reduced the leakage current of the off-state and improved the effective peak hole mobility.

Self-Induced Ge-Doped HfO2 Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O3 Treatment with GeO2 as Interfacial Layer

This study reports a self-induced ferroelectric Ge-doped HfO2 (Ge:HfO2) thin film through interface reactions. In the first experiment, three treatments for forming interfacial layer (IL) were discussed through TiN/2-nm-thick Al2O3/2-nm-thick Ge:HfO2/GeO2/Ge metal-ferroelectric-insulator-semiconductor capacitors. The remnant polarization (Pr), leakage current, and interface trap density (Dit) were compared to select the most appropriate IL treatment. The results show that the in-situ ozone treatment under the standard atomic layer deposition process had the second highest 2Pr value as well as lower Dit values. Next, the thicknesses of Al2O3/Ge:HfO2 would be changed to 4 nm/2 nm and 3 nm/3 nm to investigate the ferroelectricity and leakage current. Although the 3-nm-thick Al2O3/3-nm-thick Ge:HfO2 shows a lower 2Pr value, the leakage current is much lower than 2-nm-thick Al2O3/2-nm-thick Ge:HfO2. The self-induced ferroelectric 3-nm-thick Ge:HfO2 thin film was then applied to fabricate Ge stacked nanowires gate-all-around field-effect transistor. The results show a steep subthreshold slope of 58 mV/dec for pFET and on-off current ratio > 105 and have high potential in low-power IC applications.

Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability

This paper explores the effects of changing the device's parameters, such as the gate length (Lg), nanowire radius (r), oxide thickness (tox), and frequency (f), on the noise characteristics of dual material graded channel (DMGC) cylindrical gate all around (CGAA) FET while considering the presence and absence of interface trap charges. The performance analysis of the DMGC CGAA FET with that of the SMGC (single material graded channel) CGAA FET, is carried out while taking into account the impact of trap charges. It's noteworthy that the DMGC FET demonstrates significant advantages, with improvement in Ion/Ioff, reduction in DIBL, and SS when compared to the SMGC CGAA FET, both in the cases of without and with traps. The investigation also extends to analyse the analog/RF performance of the DMGC FET, for different type of trap charges. Furthermore, the power spectral densities of current noise (Sid) and voltage noise (Svg) are examined by varying the device dimensions and temperature. This also addresses the various sources of noise, including flicker noise (1/f), generation-recombination (G-R) noise, and diffusion noise. These types of noise have different prevalence depending on the operating frequency. At low frequencies, flicker and G-R noises dominate, while at higher frequencies, diffusion noise becomes the prominent factor impacting the device's performance. The research findings indicate that the optimal performance of the DMGC CGAA FET is achieved with smaller nanowire radius and thinner oxide thickness, regardless of trap charges. These findings offer valuable insights for improving the design and performance of DMGC CGAA FET in low power applications.

Bias-stress-stable sub-1.5V oxide thin-film transistors via synergistic composition of sol-gel quaternary high-k oxide dielectrics

A rising demand in reliable, energy-efficient, and large-area electronics, particularly in the realm of sol-gel oxide thin-film transistors (TFTs), has steered research focus away from semiconductor towards dielectrics. However, achieving both bias stability and low-voltage operation remains a significant hurdle. While typical oxide TFTs employ high-dielectric-constant (high-k) dielectrics with lowered film thickness to acquire low-voltage operation, they inevitably suffer from undesired defects at both bulk and interfacial trap sites in dielectric layer. In this study, bias-stress-stable all solution-processed oxide TFTs were demonstrated with operation voltage under 1.5 V via sol-gel quaternary high-k oxide dielectric (Al-Hf-Zr-O, AHZO). In-depth understanding of their individual contributions to dielectric performance leads to the acquisition of optimized composition ratios of AHZO with amorphous feature and outstanding dielectric performance, marked by dielectric constant (k) over 11, leakage current density (Jleak) below 10−5.5 A cm−2, and sturdy breakdown strength (EB) exceeding 5 MV cm−1. By integrating the AHZO with In-Ga-Zn-O (IGZO) layer, we achieved sub 1.5 V TFTs while maintaining excellent bias stability with threshold voltage (VTH) shift lower than 0.20 V for 3600 s. Our findings offer a detailed insight into the realm of multi-component oxide dielectrics, paving the way for miniaturization and reliability in functional devices and sensors.

Effects of gamma-ray irradiation on material and electrical properties of AlN gate dielectric on 4H-SiC

This article investigates the radiation effects on as-deposited and annealed AlN films on 4H-SiC substrates under gamma-rays. The AlN films are prepared using plasma-enhanced-atomic-layer-deposition on an n-type 4H-SiC substrate. The AlN/4H-SiC MIS structure is subjected to gamma-ray irradiation with total doses of 0, 300, and 600 krad(Si). Physical, chemical, and electrical methods were employed to study the variations in surface morphology, charge transport, and interfacial trapping characteristics induced by irradiation. After 300 krad(Si) irradiation, the as-deposited and annealed samples exhibit their highest root mean square values of 0.917 nm and 1.190 nm, respectively, which is attributed to N vacancy defects induced by irradiation. Under irradiation, the flatband voltage (V fb) of the as-deposited sample shifts from 2.24 to 0.78 V, while the annealed sample shifts from 1.18 to 2.16 V. X-ray photoelectron spectrum analysis reveals the decomposition of O-related defects in the as-deposited AlN and the formation of Al(NO x ) y compounds in the annealed sample. Furthermore, the space-charge-limits-conduction (SCLC) in the as-deposited sample is enhanced after radiation, while the barrier height of the annealed sample decreases from 1.12 to 0.84 eV, accompanied by the occurrence of the SCLC. The physical mechanism of the degradation of electrical performance in irradiated devices is the introduction of defects like N vacancies and O-related defects like Al(NO x ) y . These findings provide valuable insights for SiC power devices in space applications.

Stochasticity in ferroelectric memory devices with different bottom electrode crystallinity

This study comprehensively analyzes of the influence of bottom electrode crystallinity on the stochastic noise in ferroelectric tunnel junctions (FTJs). We perform a comparative analysis of stochastic read noise in FTJ devices with crystalline silicon (FTJc-Si) and poly-silicon (FTJpoly-Si) bottom electrodes by utilizing low-frequency noise spectroscopy and multi-frequency conductance measurements. The results indicate that FTJpoly-Si exhibits a 50 % higher read current fluctuation in the high-resistance state (HRS) at high read currents compared to FTJc-Si due to differences in interface trap density and the subsequent barrier height fluctuations. Although the crystallinity of the bottom electrode affects the noise in the HRS, the noise in the low-resistance state (LRS) remains consistent with the consequence of bulk-limited Poole-Frenkel emission. These findings clarify the relationship between bottom electrode crystallinity and stochastic noise in FTJs, providing crucial insights for the design and operation of future ferroelectric-based memory.

Ultralow-power optoelectronic synaptic transistors based on polyzwitterion dielectrics for in-sensor reservoir computing.

Bio-inspired transistor synapses use solid electrolytes to achieve low-power operation and rich synaptic behaviors via ion diffusion and trapping. While these neuromorphic devices hold great promise, they still suffer from challenges such as high leakage currents and power consumption, electrolysis risk, and irreversible conductance changes due to long-range ion migrations and permanent ion trapping. In addition, their response to light is generally limited because of "exciton-polaron quenching", which restricts their potential in in-sensor neuromorphic visions. To address these issues, we propose replacing solid electrolytes with polyzwitterions, where the cation and anion are covalently concatenated via a flexible alkyl chain, thus preventing long-range ion migrations while inducing good photoresponses to the transistors via interfacial charge trapping. Our detailed studies reveal that polyzwitterion-based transistors exhibit optoelectronic synaptic behavior with ultralow-power consumption (~250 aJ per spike) and enable high-performance in-sensor reservoir computing, achieving 95.56% accuracy in perceiving the trajectory of moving basketballs.