Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability

Abstract

This paper explores the effects of changing the device's parameters, such as the gate length (Lg), nanowire radius (r), oxide thickness (tox), and frequency (f), on the noise characteristics of dual material graded channel (DMGC) cylindrical gate all around (CGAA) FET while considering the presence and absence of interface trap charges. The performance analysis of the DMGC CGAA FET with that of the SMGC (single material graded channel) CGAA FET, is carried out while taking into account the impact of trap charges. It's noteworthy that the DMGC FET demonstrates significant advantages, with improvement in Ion/Ioff, reduction in DIBL, and SS when compared to the SMGC CGAA FET, both in the cases of without and with traps. The investigation also extends to analyse the analog/RF performance of the DMGC FET, for different type of trap charges. Furthermore, the power spectral densities of current noise (Sid) and voltage noise (Svg) are examined by varying the device dimensions and temperature. This also addresses the various sources of noise, including flicker noise (1/f), generation-recombination (G-R) noise, and diffusion noise. These types of noise have different prevalence depending on the operating frequency. At low frequencies, flicker and G-R noises dominate, while at higher frequencies, diffusion noise becomes the prominent factor impacting the device's performance. The research findings indicate that the optimal performance of the DMGC CGAA FET is achieved with smaller nanowire radius and thinner oxide thickness, regardless of trap charges. These findings offer valuable insights for improving the design and performance of DMGC CGAA FET in low power applications.