Gate-Induced Drain Leakage Reduction in Cylindrical Dual-Metal Hetero-Dielectric Gate All Around MOSFET

Abstract

In this paper, an analytical model of dual-metal hetero-dielectric (DM-HD) cylindrical gate all around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate-induced drain leakage (GIDL) current in order to improve the device reliability, band-to-band tunneling (BTBT), and OFF state leakages. The structure is based upon asymmetric gate oxide structure by combining silicon dioxide (SiO2) gate dielectric at source side and vacuum dielectric at drain side, which significantly reduces BTBT and OFF-state gate leakages, thereby making it suitable for low-power applications. It is examined that GIDL i.e., an OFF-state leakage phenomenon, is reduced in DM-HD GAA MOSFET by lowering the BTBT. This can be done by reducing OFF-state leakages due to: 1) increase in tunneling width and 2) increased barrier height from source to channel. The results show that the OFF-state leakage current in DM-HD GAA MOSFET reduces to an order of $10^{-\textsf {13}}$ over $10^{-\textsf {9}}$ A as in the case of conventional GAA MOSFET. The results so obtained are compared with those of cylindrical dual-metal GAA (DM-GAA) MOSFET and GAA MOSFET to analyze its performance. OFF-state leakages at higher temperatures have also been analyzed.