Interface State Density Values Research Articles

A Wide Frequency Range C-V and G-V Characteristics Study in Schottky Contacts with a BODIPY-Pyridine Organic Interface

In this study, it was aimed to produce an organic interface layered Schottky diode structure and frequency effect on capacitance-conductance-voltage measurements. In this context, phosphor doped n-type Si single crystal has been used as a semiconductor substrate with a 1-20 Ω.cm resistivity, (100) surface oriention, 2 inches in diameter and 350 μm thickness. The (E)-5,5-difluoro-1,3,7,9-tetramethyl-10-phenyl-2-(2-(pyridin-2-yl)vinyl)-5H-54,64-dipyrrolo [1,2-c:2',1'-f] [1,3,2] diazaborinine (BODIPY-Pyridine) thin film was coated on n-Si using the spin coating technique.
 Ohmic and rectifier contacts were coated by evaporation of indium (In) and gold (Au) using a thermal evaporation system and Au/ BODIPY-Pyridine/n-Si/In Schottky diode was fabricated. Capacitance-voltage (C-V) and conductance-voltage (G-V) measurements of this structure were gained at different frequencies in the dark. Contingent on the frequency, the series resistance (Rs) and the interface state density (Nss) values were identified by using the conductance and Hill-Coleman method, respectively.

Preparation of high specific surface mPSi/Al2O3/ZnO microcapacitors

In this study, a new concept is explored for an electrolyte-free microcapacitor fabrication based on mesoporous silicon (mPSi) and zinc oxide (ZnO) electrodes, separated by aluminum oxide (Al2O3) as a dielectric layer. For this conception, we gathered various techniques in order to have the best system, namely: •Electrochemical etching to form mPSi.•Aluminum (Al) thin film deposited on mPSi by physical vapor deposition (PVD).•Oxidation of Al in a rapid thermal processing (RTP) furnace heated to 600 °C under pure oxygen gas injection for 300 s.•Coating the ZnO layer on the assembly electrochemically. The designed device was characterized under DC and AC currents with a specific capacitance of 160 nF/cm2 for a DC of 40 nA/cm2, low series resistance (38.7 Ω) and high ohmic resistance (1.69 MΩ). The latest value of Rox indicates a very high ohmic resistance across the Al2O3 dielectric layer. The studied device shows good stability for galvanoplastic charge–discharge cycles exceeding 1200 cycles with an efficiency of about 60%. In AC, the decrease of the capacitance values with a frequency increase indicates the presence of numerous charge traps near the interface of Al2O3 with the electrodes. The conductance measurements demonstrate a high interface state density (Nss) value of 1.6 × 1012 cm−2. The calculated leakage current was about two to three times higher than that obtained in the literature.

Investigation of the Electrical Properties of PAN-GO/p-Si Schottky Diode

In this article, the electrical properties of PAN-GO/p-Si Schottky diode were investigated in the dark at room temperature. Field-emission scanning electron microscopy (FE-SEM) was utilized to study the structure of the PAN:GO interfacial layer. Diode parameters were calculated according to thermionic emission theory. By using the I-V characteristic of the prepared PAN-GO diode, the ideality factor (n), barrier height (ФB) and series resistance (Rs) values were evaluated with the I-V method and Norde functions. The barrier height values calculated with the I-V and Norde function were found to be 0.767 eV and 0.761 eV, respectively. The ideality factor was found to be 2.078 from the I-V method. The series resistance value of the diode was calculated as 42 kΩ using Norde functions. Energy-dependence profile of interface state density was determined from the current-voltage characteristics by considering the voltage-dependence of barrier height and ideality factor The interface state density (Nss) values of the PAN-GO/p-Si Schottky diode are 9.5x1011 eV-1cm-2 for 0.35-Ev eV and 1.03x1011 eV-1cm-2 for 0.74-Ev eV. Experimental results approved that the PAN-GO interfacial layer improved the performance of metal-semiconductor Schottky diode in respect of low ideality factor, interface state density, and high barrier height and rectification rate.

(Invited) Study of HfO2-Based High-k Gate Insulators for GaN Power Device

Gallium nitride (GaN) high-electron-mobility transistor and vertical GaN devices with metal-oxide-semiconductor (MOS) structure have been widely investigated to suppress leakage currents for applications associated with high power and high frequency [1-3]. Metal oxide (High-k) with a high dielectric constant (k)-value have been employed instead of SiO2 from the viewpoint of increasing the physical thickness [4, 5]. HfO2-based materials including HfO2, HfSiOx and HfAlOx are the candidate materials because of its relatively large bandgap (~6.5 eV) and a high k value (> 13) [6-9]. These films for transistor applications are typically fabricated using atomic layer deposition (ALD) because ALD is compatible with semiconductor fabrication process and has a big advantage of conformal film fabrication on three-dimensional structure. In this study, we report comparison of characteristics among HfO2, HfSiOx and HfAlOx gate insulators of GaN MOS capacitors.Pt-gated n-GaN MOS capacitors with HfO2, HfSiOx and HfAlOx gate insulators were prepared as follows. A single HfO2 layer, (HfO2)m/(SiO2)n and (HfO2)m/(Al2O3)n nanolaminate layers were deposited on n+-GaN/n-GaN epilayer by plasma-enhanced ALD at 300°C. The m/n ratio was kept at 2/1. Next, PDA was carried out at 800°C in N2. HfSiOx and HfAlOx films were formed from (HfO2)m/(SiO2)n and (HfO2)m/(Al2O3)n nanolaminate after PDA, respectively. The thicknesses of these films were ~24 nm. Finally, Pt gate electrode was deposited on gate insulator and Pt/Ti ohmic contact was deposited on the n-GaN substrate.The HfSiOx and HfAlOx films had an amorhous structure while HfO2 film had a polycrystalline structure after PDA at 800°C using transmission electron microscopy and electron diffraction pattern analysis. The HfO2 capacitor exhibited a small breakdown electric field (EBD) value of 2.6 MV/cm, defined at a current density of 1.0 × 101 A/cm2, because leakage currents easily flow along grain boundaries of the polycrystalline structure. On the other hand, the EBD values of the HfSiOx and HfAlOx capacitors increased up to 8.5 MV/cm. From capacitance-voltage measurements, the estimated k values of the HfO2, HfSiOx and HfAlOx films were 17.7, 17.2 and 13.5, respectively, as expected. The flatband voltage hysteresis (620 mV) of the HfO2 capacitor was much larger than those (~10 mV) of the HfSiOx and HfAlOx capacitors, indicating that the number of charge trapping/detrapping sites and frequency responsive defects was significantly decreased in the HfSiOx and HfAlOx capacitors. No frequency dispersion of the HfSiOx and HfAlOx capacitors were observed while the HfO2 capacitor showed a large frequency dispersion. The interface state density (Dit) values at Ec - E = 0.25 eV which estimated using the conductance method of the HfSiOx (~1 × 1011cm-2V-1) and HfAlOx (4.4 × 1011cm-2V-1) capacitors were one magnitude lower than that of the HfO2 capacitor (3.1 × 1012cm-2V-1), indicating that the electrical defects at n-GaN/HfSiOx and n-GaN/HfAlOx interfaces were much less than that of the n-GaN/HfO2 interface.We conclude that the HfSiOx and HfAlOx were the attractive materials as gate insulator because of amorphous structure, higher k, relatively low Dit, and high Ebd.This work was supported by JSPS KAKENHI (Grant No. JP20H02189). A part of this work was also supported by the MEXT “Program for research and development of next-generation semiconductor to realize energy-saving society.” Program Grant Number JPJ005357. The authors wish to thank Dr. A. Ohi, Dr. N. Ikeda, and the members of the nanofabrication group of the National Institute for Materials Science for their support during this study.[1] M. Kodama et al., Appl. Phys. Express 1, 021104 (2008).[2] Z. Yatabe et al., J. Phys. D: Appl. Phys. 49, 393001 (2016).[3] T. Oka et al., Appl. Phys. Express 8, 054101 (2015).[4] T. Hashizume et al., Appl. Phys. Express 11, 124102 (2018).[5] T. Kikuta et al, J. Vac. Sci. Technol. A 35, 01B122 (2017).[6] T. Nabatame et al., Appl. Phys. Express 12, 011009 (2019).[7] E. Maeda et al., Microelectron. Eng. 216, 111036 (2019).[8] R. Ochi et al., AIP Advances 10, 065215 (2020).[9] S. Miyazaki et al., ECS Trans. 92, 11(2019).

Passivation of n- and p-Type Silicon Surfaces With Spray-Coated Sol-Gel Silicon Oxide Thin Film

Thermally grown SiO2 is widely used for silicon surface passivation in solar cells and other applications due to excellent interfacial properties. SiO2 films with thickness in the range of 17 nm deposited by industrially viable spray-coating technique on both n- and p-type silicon are reported. Low values of interface state density of ${1.4}\times {10}^{{10}}$ cm $^{\boldsymbol -{2}}$ eV $^{\boldsymbol -{1}}$ on n-type and ${2.0}\times {10}^{{10}}$ cm $^{\boldsymbol -{2}}$ eV $^{\boldsymbol -{1}}$ on p-type were achieved. Fixed oxide charges in the range of 7.1– ${9.4}\times {10} ^{{11}}$ cm $^{\boldsymbol -{2}}$ and 3.9– ${6.5}\times {10} ^{{11}}$ cm $^{\boldsymbol -{2}}$ on n- and p-type, respectively, are obtained. Excellent passivation results in the effective surface recombination velocity of 0.97 cms $^{\boldsymbol -{1}}$ and 8.07 cms $^{\boldsymbol -{1}}$ at minority carrier concentration of $10^{{15}}$ cm $^{\boldsymbol -{3}}$ on n- and p-type Czochralski silicon, respectively, without the use of capping layer. SiO2 film exhibits dielectric breakdown field strength of 4.3 MVcm $^{\boldsymbol -{1}}$ and 5.6 MVcm $^{\boldsymbol -{1}}$ and leakage current density of ${2.2}\times 10 ^{\boldsymbol -{8}}$ Acm $^{\boldsymbol -{2}}$ and ${1.1}\times {10} ^{\boldsymbol -{8}}$ Acm $^{\boldsymbol -{2}}$ at 1 MVcm $^{\boldsymbol -{1}}$ on n- and p-type silicon, respectively. These values are superior to sol-gel-based SiO2 films reported previously and are comparable to or better than those reported for other methods for the growth or deposition of SiO2 on silicon. Amorphous nature of the film is validated by high-resolution transmission electron microscopy (TEM). The X-ray photoelectron spectroscopy (XPS) analysis shows nearly stoichiometric SiO x film.

Photovoltaic, capacitance-voltage, conductance-voltage, and electrical impedance characteristics of p-type silicon/intrinsic-silicon/n-type semiconducting iron disilicide heterostructures built via facing target direct-current sputtering

p-Type silicon (Si)/intrinsic Si/n-type semiconducting iron disilicide heterostructures were built via facing target direct-current sputtering. To assess the photovoltaic properties, the current density-voltage characteristic curves were recorded in conditions of dark and under irradiation via an Air Mass 1.5 solar simulator (100 mW/cm2). The built heterostructures demonstrated effective rectifying behavior along with a rather substantial leakage current. The open-circuit voltage and the short-circuit photocurrent density values were 178.00 mV and 10.08 mA/cm2, respectively. The assessed energy conversion efficiency was approximately 0.75%. The series resistance (Rs) values at 0 V appraised by the Nicollian-Goetzberger technique were 60.28 Ω at 2 MHz, and 4.13 × 103 Ω at 10 kHz. Their interface state density values evaluated through the Hill-Coleman method were 1.38 × 1012 cm−2/eV at 10 kHz and 1.31 × 1011 cm−2/eV at 2 MHz. The Rs and interface states occurring in the heterostructure interface zone should be the potential determinant of the degeneration of the photovoltaic properties. The characteristics of the real (Z’) and imaginary components of impedance under the changing voltages manifested a shape of one semicircle having a semicircular midpoint beneath the Z’ coordinate. An equivalent circuit model that was related with the heterostructure behavior should be assembled from the parallel association of resistance and constant phase element connected with Rs.

Electrical properties of Graphene/Silicon structure with Al2O3 interlayer

The electrical properties of the fabricated Al/Gr/Al2O3/p-Si structure have been analyzed using frequency-dependent capacitance/conductance–voltage (C/G–V) measurements. Graphene (Gr) nanosheets were grown on to copper (Cu) catalyst substrate, which has 99.99% purity, by Chemical Vapor Deposition (CVD) technique, and then the Graphene was transferred on Al2O3/p-Si by the standard transfer process. The Graphene structures have been characterized by Raman Spectroscopy and Transmission Electron Microscopy (TEM) analyses, and the results of both analyses confirmed the monolayer/bilayer Graphene nanostructure. The forward and reverse bias G–V and C–V measurements of this structure have been performed in 10 kHz–400 kHz and at 300 K. The frequency dispersion in C and G can be evaluated for interface state density ( $$D_{{{\text{it}}}}$$ ) and series resistance ( $$R_{{\text{s}}}$$ ) values. The values of $$D_{{{\text{it}}}}$$ and $$R_{{\text{s}}}$$ are dependent on frequency and increase with decreasing frequency. The $$R_{{\text{s}}} - V$$ graph shows a peak form at all frequencies in the depletion region and vanishes with increasing frequency. The obtained results suggest that the prepared structure can be used in electronic device applications.

C-V-f and G/ω-V-f characteristics of Au/(In2O3-PVP)/n-Si (MPS) structure

In this work, the indium oxide (In2O3)-polyvinylpyrrolidone(PVP) film on the n-Si substrate was coated by a spin coating method. Thus, the Au/(In2O3-PVP)/n-Si metal-polymer-semiconductor (MPS) structure was fabricated. The capacitance/conductance-voltage-frequency (C-V-f and G/ω-V-f) characteristics of the fabricated MPS structure have been analyzed in the frequency range of 10 kHz - 1 MHz. The series resistance (Rs) and interface state density (Nss) value of the MPS structure were determined by using the conductance and Hill-Coleman method, respectively. In addition, other electronic parameters such as the diffusion potential, barrier height, depletion layer width, and surface potential were extracted from the C−2-V characteristics.

Photovoltaic Properties and Series Resistance of p-Type Si/Intrinsic Si/n-Type Nanocrystalline FeSi₂ Heterojunctions Created by Utilizing Facing-Targets Direct-Current Sputtering.

p-Type Si/intrinsic Si/n-type nanocrystalline iron disilicide heterojunctions were created by utilizing facing targets direct-current sputtering at the pressure of 1.33×10-1 Pa that investigated the photovoltaic properties. They exhibited a large leakage current and a small energy conversion efficiency of 0.62%. From using the method of Nicollian and Brews, the series resistance (Rs) values at zero bias voltage were 7.40 Ω at 2 MHz and 7.57 Ω at 50 kHz, respectively, which were in agreement with that estimated by the means of Norde. From applying the method of Hill-Coleman, the interface state density (nss) values were 3.15×1015 cm-2 eV-1 at 50 kHz and 8.93×1013 cm-2 eV-1 at 2 MHz. The obtained results revealed the presence of Rs and nss at the junction interface, which should be the potential cause of spoiled photovoltaic performance in the heterojunctions.

Heterointerface properties of diamond MOS structures studied using capacitance–voltage and conductance–frequency measurements

The interface properties of Al2O3/hydrogen-terminated diamond (H-diamond) metal-oxide-semiconductor (MOS) structures both with and without NO2 p-type doping were studied by measuring the capacitance–voltage (C-V) and conductance–frequency (G–f) characteristics to investigate the effect of NO2 p-type doping at the Al2O3/H-diamond interface. The interface state density was studied by measuring the conductance as a function of frequency and applied voltage. Interface state density (Dit) values are for NO2 p-doped MOS structure varied from ~5.7 × 1012 cm−2 eV−1 at 0.27 eV above the valence band maximum (VBM) to 1.75 × 1012 cm−2 eV−1 at 0.36 eV above VBM. Conversely, MOS structure without NO2 p-type doping exhibits a Dit value of approximately 4.2 × 1012 cm−2 eV−1 within an energy range of 0.27 to 0.39 eV. In addition, border trap density in the Al2O3 layer near the interface is also discussed.

The current–voltage and capacitance–voltage characterization of the Au/Methylene Blue/n-GaAs organic-modified Schottky diodes

We report the electrical properties of the Au/n–GaAs devices with and without thin organic interface layer. Methylene blue (MB) is a heterocyclic aromatic chemical compound with the molecular formula C16H18N3SCl. The MB layer was formed by spin coating technique on chemically cleaned gallium arsenide (GaAs) substrate. The current–voltage (I–V) and the frequency dependent capacitance–voltage (C–V) characteristics of the Au/MB/n–GaAs metal-insulator-semiconductor (MIS) and Au/n–GaAs metal-semiconductor (MS) devices have been investigated at room temperature. The MS and MIS devices I–V characteristics the showed a good rectification, and they were analyzed based on the thermionic emission (TE) theory. The ideality factor (n) and the barrier height (Φb(IV)) from the I–V characteristics was determined as 1.131±0.006 and 0.782±0.005 eV for MS device and 1.336±0.057 and 0.950±0.008 eV for MIS device, respectively. A Cheung’s method and modified Norde's function has been used to extract the parameters including the (Φb) and the series resistance (RS). Also the values of the barrier height obtained from the C–V measurements (Φb(CV)) of the MS and MIS was 0.863±0.034 eV and 1.187±0.093 eV, at 1 MHz, respectively.Distributions of the interface state density (Dit) of the MS and MIS devices were derivate from I–V and C–V measurements. Our results indicates that the Au/MB/n–GaAs device had lower interface state density values than the Au/GaAs device. Also non-saturated reverse bias current investigated by the using a Pole-Frenkel emission model. Furthermore, the optical and morphological properties of MB layer were investigated by the Atomic Force Microscopy (AFM), Scanning Electron Microscopy (SEM) and UV-vis Spectrophotometer (UV-vis).Finally, we showed that, increasing Φb and decreasing Dit and improving electrical parameters of MIS devices indicates that, thin MB interface layer could prefer for modification of Au/n–GaAs devices.

Analysis of Schottky Barrier Parameters and Current Transport Properties of V/p-Type GaN Schottky Junction at Low Temperatures

The electrical characteristics of a V/p-GaN Schottky junction have been investigated by current–voltage (I–V) and capacitance–voltage (C–V) characteristics under the assumption of the thermionic emission (TE) theory in the temperature range of 120–280 K with steps of 40 K. The zero-bias barrier height (ΦB0), ideality factor (n), flat-band barrier height (ΦBF) and series resistance (RS) values were evaluated and were found to be strongly temperature dependent. The results revealed that the ΦB0 values increase, whereas n, ΦFB and RS values decrease, with increasing temperature. Using the conventional Richardson plot, the mean barrier height (0.39 eV) and Richardson constant (8.10 × 10−10 Acm−2 K−2) were attained. The barrier height inhomogeneities were demonstrated by assuming a Gaussian distribution function. The interface state density (NSS) values were found to decrease with increasing temperature. The reverse leakage current mechanism of the V/p-GaN Schottky junction was found to be governed by Poole–Frenkel emission at all temperatures.

The Effect of Thermal Annealing and Measurement Temperature on Interface State Density Distribution and Time Constant in Ni/n-GaP Rectifying Contacts

The capacitance–frequency (C–f) and conductance–frequency (G–f) characteristics of the as-deposited and 400°C annealed Ni/n-GaP/Al diode were measured in a temperature range of 100–320 K with steps of 20 K. The values of interface state density Nss and their time constant were obtained from the temperature-dependent C–f and G–f characteristics in the measurement frequency range of 5.0 kHz to 5 MHz. The effect of annealing and measurement temperature on Nss and time constant of a Ni/n-GaP Schottky diode were analyzed from the forward bias voltage to the reverse bias voltage − 0.60 with steps of 0.30 V. The Nss value ranges from 8.8 × 1011 cm−2eV−1 at 0.60 V to 5.71 × 1011 cm−2eV−1 at − 0.60 V for the as-deposited diode, and 1.3 × 1012 cm−2eV−1 at 0.60 V to 5.5 × 1011 cm−2eV−1 at − 0.60 V for the 400°C annealed diode at a measurement temperature of 300 K. The interface state density value increases with high measurement temperature for the as-deposited and annealed diode.

Performance Enhancement for Charge Trapping Memory by Using Al2O3/HfO2/Al2O3 Tri-Layer High-κ Dielectrics and High Work Function Metal Gate

In this work, we have fabricated and systematically characterized a type of charge trapping memory (CTM) device with Al2O3/HfO2/Al2O3 tri-layer high-κ dielectric stacks and high work function tungsten metal gate (named as MAHAS in short). The extracted interface state density (Dit) value for the MAHAS memory is comparatively low owing to the optimized high-κ/Si interface quality using SiO2 ultrathin film (∼10 Å) grown by deionized water/O3. The MAHAS memory devices demonstrate desirable memory effects, especially significantly improved program and erase (P/E) speed. A large hysteresis memory window of 5.4 V by ± 10 V sweeping voltage and ∼2.7 V flat-band voltage shift by programming at +7 V for 100 μs are obtained. With respect to memory reliability, the MAHAS memory shows negligible memory window degradation after 106 P/E cycles, and the memory window retains 72.4% of the originally stored charge even after 105 s’ retention. With the simple structure and improved operation efficiency, the proposed MAHAS memory device is promising for future nonvolatile charge trapping memory applications.

Improvement of diode parameters in Al/n-Si Schottky diodes with Coronene interlayer using variation of the illumination intensity

In present work, Coronene thin films on Si wafer have been deposited by the spin coating method. It has been ultimately produced Al/Coronene/n-Si/In Schottky diode. Current–voltage (I-V) measurements have been used to determine the effect of illumination intensity in the Schottky diodes. The barrier height (ΦB) values increased as ideality factor (n) values decreased with a increase in illumination intensity. The ΦB values have been found to be 0.697 and 0.755eV at dark and 100mW/cm2, respectively. The n values have been found to be 2.81 and 2.07 at dark and 100mW/cm2, respectively. Additionally, the series resistance (Rs) values from modified Norde method and interface state density (Nss) values using current-voltage measurements have been determined. The values of Rs have been found to be 1924 and 5094Ω at dark and 100mW/cm2, respectively. The values of Nss have been found to be 4.76 × 1012 and 3.15 × 1012eV−1cm−2 at dark and 100mW/cm2, respectively. The diode parameters are improved by applying the variation of illumination intensity to the formed Schottky diodes.

Interface states study of intrinsic amorphous silicon for crystalline silicon surface passivation in HIT solar cell**Project supported by the National Natural Science Foundation of China (Grant Nos. 51361022 and 61574072) and the Postdoctoral Science Foundation of Jiangxi Province, China (Grant No. 2015KY12).

Intrinsic hydrogenated amorphous silicon (a-Si:H) film is deposited on n-type crystalline silicon (c-Si) wafer by hot-wire chemical vapor deposition (HWCVD) to analyze the amorphous/crystalline heterointerface passivation properties. The minority carrier lifetime of symmetric heterostructure is measured by using Sinton Consulting WCT-120 lifetime tester system, and a simple method of determining the interface state density from lifetime measurement is proposed. The interface state density measurement is also performed by using deep-level transient spectroscopy (DLTS) to prove the validity of the simple method. The microstructures and hydrogen bonding configurations of a-Si:H films with different hydrogen dilutions are investigated by using spectroscopic ellipsometry (SE) and Fourier transform infrared spectroscopy (FTIR) respectively. Lower values of interface state density are obtained by using a-Si:H film with more uniform, compact microstructures and fewer bulk defects on crystalline silicon deposited by HWCVD.

Effect of oxide traps on channel transport characteristics in graphene field effect transistors

A semiempirical model describing the influence of interface states on characteristics of gate capacitance and drain resistance versus gate voltage of top gated graphene field effect transistors is presented. By fitting our model to measurements of capacitance–voltage characteristics and relating the applied gate voltage to the Fermi level position, the interface state density is found. Knowing the interface state density allows us to fit our model to measured drain resistance–gate voltage characteristics. The extracted values of mobility and residual charge carrier concentration are compared with corresponding results from a commonly accepted model which neglects the effect of interface states. The authors show that mobility and residual charge carrier concentration differ significantly, if interface states are neglected. Furthermore, our approach allows us to investigate in detail how uncertainties in material parameters like the Fermi velocity and contact resistance influence the extracted values of interface state density, mobility, and residual charge carrier concentration.

Organic photodetector with coumarin-adjustable photocurrent

Drop casting technique was used to fabricate Al/p-Si/coumarin doped fullerite/Al diodes. The effects of coumarin doping on the photoresponse properties of the diodes were investigated. The forward bias current of the diodes increases exponentially with voltage confirming rectification behavior. The reverse current of the diodes increases with increasing illumination intensities. The photocurrent of the diodes is higher than the dark current. The obtained m value indicates that the photocurrent exhibited a linear photoconducting behavior. The coumarin doped fullerite diodes indicate a non-ideal behavior with obtained ideality factors. The obtained barrier height value of the Al/p-Si/coumarin doped fullerite/Al diode is comparable to that of the conventional Al/p-Si (ϕb=0.58eV) Schottky diode. The measured values of the capacitance decrease with the increasing frequency. The decrease in capacitance was explained on the basis of interface states. It was concluded that the obtained barrier height and interface state density values of the diode are modified doping fullerite with coumarin. The obtained results suggest that the fabricated diodes could be used as an optical sensor in various optoelectronic applications.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-κ TiO2 thin films have been fabricated from a facile, combined sol – gel spin – coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index ‘n’ quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 Å. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance – voltage (C – V) and deep level transient spectroscopy (DLTS). The flat – band voltage (VFB) and the density of slow interface states estimated are – 0.9, – 0.44 V and 5.24×1010, 1.03×1011 cm−2; for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross – sections measured by DLTS are EV + 0.30, EC – 0.21 eV; 8.73×1011, 6.41×1011 eV−1 cm−2 and 5.8×10−23, 8.11×10−23 cm2 for the NMOS and PMOS structures, respectively. A low value of interface state density in both P- and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent.

The interface state density characterization by temperature-dependent capacitance–conductance–frequency measurements in Au/Ni/n-GaN structures

We have fabricated the Au/Ni/n-GaN structures and measured their capacitance–frequency (C–f) and conductance (G/w)-angular frequency (w) characteristics in the temperature range of 60–320 K. The C–f curves for different reverse bias voltages have shown a behavior almost independent of the bias voltage at frequencies above 300 kHz at each measurement temperature. We have calculated the temperature-dependent interface state density, Nss, values from the G/w versus w curves. The Nss value for the Ni/n-GaN interface ranges from 3.36 × 1011 cm−2 eV−1 at 0.0 V to 2.92 × 1011 cm−2 eV−1 at 0.40 V for 60 K, and 6.63 × 1011 cm−2 eV−1 at 0.0 V to 3.87 × 1011 cm−2 eV−1 at 0.40 V for 320 K. That is, the interface state density value increases with increasing temperature. It has been seen that the values of Nss obtained from the G/w versus w curves of the device are lower than the given values for metal/n-type GaN interface in the literature.