Abstract
High-κ TiO2 thin films have been fabricated from a facile, combined sol – gel spin – coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index ‘n’ quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 Å. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance – voltage (C – V) and deep level transient spectroscopy (DLTS). The flat – band voltage (VFB) and the density of slow interface states estimated are – 0.9, – 0.44 V and 5.24×1010, 1.03×1011 cm−2; for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross – sections measured by DLTS are EV + 0.30, EC – 0.21 eV; 8.73×1011, 6.41×1011 eV−1 cm−2 and 5.8×10−23, 8.11×10−23 cm2 for the NMOS and PMOS structures, respectively. A low value of interface state density in both P- and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent.
Highlights
The activation energies, interface state densities and capture cross – sections measured by deep level transient spectroscopy (DLTS) are EV + 0.30, EC – 0.21 eV; 8.73×1011, 6.41×1011 eV−1 cm−2 and 5.8×10−23, 8.11×10−23 cm[2] for the NMOS and PMOS structures, respectively
Very low value of capture cross – section for both the carriers due to their amphoteric nature indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent
The flat – band voltage (VFB) and the density of slow interface states estimated are – 0.9, – 0.44 V and 5.24×1010,1.03×1011 cm−2 for the NMOS and PMOS structures, respectively
Summary
Such as reliability and mobility degradation.[22] Deep – level transient spectroscopy (DLTS) allows an estimation of density of localized states, position in Si band gap and their capture cross – sections at the oxide – semiconductor interface with improved accuracy than the capacitance – voltage and conductance technique. In metal – oxide – semiconductor (MOS) structures, the DLTS method consists of filling the interface trap during the pulse, analyzing the emission rate during a temperature scan.[23,24,25]. Made films were characterized and found to have good quality, further TiO2 films have been incorporated in to the MOS structure for electrical characterization. The TiO2/Si interface state density (Dit), capture cross – section (σp) of traps present has been investigated by sensitive DLTS technique
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