Interconnect Parasitics Research Articles

Analysis of Delay and Dynamic Crosstalk in Spatially Arranged Mixed CNT Bundle Interconnects at Different Technology Nodes

In the present nanoscale regime, mixed carbon nanotube bundles (MCBs) are considered to be highly promising interconnect options. This research paper introduces a spatially arranged mixed carbon nanotubes (CNTs) bundle (MCB), wherein single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs) occupy equal halves in the MCB. An equivalent single conductor (ESC) model for MCB is employed to analyze the interconnect performances in terms of signal transmission delay and dynamic crosstalk delay at different technology nodes (i.e., 32nm, 22nm, and 16 nm). Encouragingly, a significant reduction in signal transmission delay and dynamic crosstalk induced delay are observed at 32 nm technology node. It is observed that at 32 nm technology node, the propagation delay and crosstalk induced delay significantly improves by 29.40% and 55.53%, respectively, compared to 22 nm technology node and 187.88% and 185.94%, respectively, compared to 16 nm technology node. The improvement in interconnect performances can primarily be attributed to the improvement in the number of conducting channels inside the MCB at 32 nm, which greatly impacted the interconnect parasitics such as quantum resistance, quantum capacitance, kinetic inductance etc.

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network

The performance of analog and RF circuits is widely affected by the interconnection parasitic in the circuit. With the progress of technology, interconnection parasitics plays a larger role in performance deterioration. To solve this problem, designers must repeat layout design and validation process. In order to achieve an upgrade in the design efficiency, in this paper, a Graph Neural Network (GNN)-based pre-layout parasitic parameter prediction method is proposed and applied to the design optimization of a 28 nm PLL. With the new method adopted, the frequency band overlap rate of the VCO is improved by 2.3 percents for an equal design effort. Similarly, the optimized CP is superior to the traditional method with a 15 ps mismatch time. These improvements are achieved under the premise of greatly saving the optimization iteration and verification costs.

Effects of underfill on wideband flip-chip packaging for 5G millimeter-wave applications

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

Photocurrent-Summation-Based High-Speed Integrated Photonic Digital-to-Analog Converter

Achieving ultra high-speed arbitrary signal generation with conventional electronic digital-to-analog converters (DACs) is becoming extremely challenging, owing to the inherent bandwidth limitations due to interconnect and device parasitics in electronic circuits. Using optical techniques, and leveraging the advantages of photonic integration, a power-efficient solution for high-speed high-precision digital-to-analog conversion is proposed. A framework presenting resolution, power consumption and bandwidth tradeoffs for performance analysis of the photonic digital-to-analog converter (PDAC) with different configurations, is shown. The proposed PDAC concept is demonstrated in a proof-of-concept experimental setup, generating multi-level signals at up to 21.5 GBd.

NEAT: Nonlinearity Aware Training for Accurate, Energy-Efficient, and Robust Implementation of Neural Networks on 1T-1R Crossbars

In this era of IoT, energy-efficient and adversarially secure implementation of deep neural networks (DNNs) on hardware has become imperative. Memristive crossbars have emerged as an energy-efficient component of deep learning hardware accelerators due to their compact and efficient matrix-vector multiplication (MVM) implementation. However, they suffer from nonidealities (such as, interconnect parasitics, device variations, and sneak paths) introduced by their circuit topology that degrades computational accuracy. A 1T-1R synapse, adding a transistor (1T) in series with the memristive synapse (1R), has been proposed to mitigate sneak paths in a crossbar. However, we observe that the nonlinear characteristics of the transistor affect the overall conductance of the 1T-1R cell which in turn affects the MVM operation. This 1T-1R nonlinearity arising from the input voltage-dependent nonlinearity is not only difficult to model or formulate, but also causes a drastic performance degradation of DNNs when mapped to such crossbars. In this article, we first analyses the nonlinearity in ideal 1T-1R crossbars (excluding nonidealities, such as device variations and interconnect parasitics) and propose a novel nonlinearity aware training (NEAT) method to address the nonlinearities. Specifically, we first identify the range of network weights, which can be mapped into the 1T-1R cell within the linear operating region of the transistor. After that, we regularize the weights of neural networks to exist within the linear operating range by using an iterative training algorithm. Our iterative training significantly recovers the classification accuracy drop caused by the nonlinearity. Moreover, we find that each layer has a different weight distribution and in turn requires different gate voltage of transistor to guarantee linear operation. Based on this observation, we achieve energy efficiency while preserving classification accuracy by applying heterogeneous gate-voltage control to the 1T-1R cells across different layers. Finally, we conduct various experiments on CIFAR10 and CIFAR100 benchmark datasets to demonstrate the effectiveness of our NEAT. Overall, NEAT yields <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 20\%$ </tex-math></inline-formula> energy gain with less than 1% accuracy loss (with homogeneous gate control) when mapping ResNet18 networks on 1T-1R crossbars. Thereafter, we integrate the 1T-1R crossbars with various nonidealities. We show that NEAT leads to more adversarially robust mappings of DNNs onto nonideal 1T-1R crossbars than standard DNNs mapped directly onto 1R crossbars. In case of a VGG11 network on CIFAR100 dataset, we obtain <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 17$ </tex-math></inline-formula> % improvement in clean accuracy and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2$ </tex-math></inline-formula> %–8% & <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 5$ </tex-math></inline-formula> %–6% improvements in adversarial accuracies, respectively, for fast gradient sign method (FGSM) and projected gradient descent (PGD)-based adversarial attacks via NEAT on nonideal 64 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 64 crossbars, in comparison to standard DNNs.

System on Chip Noise Integrity Simulation

In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.

Analysis of Parasitic Effects in a Crossbar in CMOS Based Neuromorphic System for Pattern Recognition Using Memristive Synapses

This paper proposes a complete CMOS realized neuromorphic system for pattern recognition having CMOS-based memristor emulators as synaptic circuits. The crossbar array of the system is modeled by considering the emulator circuit&#x0027;s area to determine the spacing between the interconnects. The interconnect parasitics are obtained from the ANSYS Q3D extractor. Parasitics extracted are also validated using the analytical model. A crossbar array architecture modeled with the extracted parasitic components and the memristor emulator will provide an understanding of the behavior of the crossbar array and can be used to analyze the parasitic effects on various real-time applications. Our analysis shows that as the operating frequency increases, the recognition rate of the neuromorphic system is reduced by 66.67&#x0025; due to the crossbar&#x0027;s parasitics, non-idealities of the neuron, and memristor circuits. The memristor&#x0027;s state, either low or high resistance, significantly affects the system&#x0027;s performance, which is evaluated by the rise time and signal delay. The energy consumed by the CMOS-based memristor emulator synapse for recognizing each pattern is 0.44 &#x00A0;<inline-formula><tex-math notation="LaTeX">$nJ$</tex-math></inline-formula>, which is significantly lower when compared with the previous works. The circuit design and verification are done using 180-nm CMOS technology.

Novel Physics-Based Small-Signal Modeling and Characterization for Advanced RF Bulk FinFETs

A novel RF small-signal model in the form of a physics-based equivalent circuit for advanced bulk FinFETs is proposed. Based on the unique multifin structure, parallel resistance–capacitance branches are introduced to account for the gate–source and gate–drain admittances. The deembedding is carefully performed after its effectiveness is verified by accurately modeling the pad and interconnect parasitics. An analytical method is developed to directly extract the model parameters from measurements. The model is validated in 7 and 14 nm bulk FinFET technologies, and the modeled results show an excellent agreement with the measured data up to 50 GHz ( $\!\sim \!~{f} _{\mathbf {T}} \boldsymbol /4$ ). The dependencies of FinFET RF performances on the layout dimensions are investigated, and they are compared between the two advanced FinFET technologies.

A prominent approach to design low noise amplifiers for 802.11 wireless receiver frontends

With the efforts of innovative consortium, wireless local area network (WLAN) became alternative standard in wireless local area networking applications. From the beginning the data rate keeps pace from mega bits per second (Mbps) up to giga bits per second. The ease of adaptability of WLAN protocol and the need for high data rate communication system made a reason to develop a solution and to incorporate real time wireless transceivers on network interface cards and FPGAs. Over the past decade, the RFIC technology became the hive of communication industry, with the proliferation of 802.11 a, g, n, ac, ad wireless protocols. The applications like ultra wide band (UWB), digital TV broadcasting and global positioning system found their way to main-stream gadgets. With the design preferences such as interconnect parasitics, interconnects and coupling between devices the passive elements must be precisely designed. In this article, novel requirements of low noise amplifier (LNA) design for 2.4 GHz application with noise modelling is presented.

Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects

Rigorous technology scaling of integrated circuits to nanometer range aids to acquire prodigious operational speed and versatile functionality in system-on-chip. However, this leads to escalation in interconnect parasitics and non-ideal issues that have become primary bottleneck in the existing copper based on-chip interconnect system. Graphene based carbon nanotube bundle has emerged as prospective interconnect for high speed applications. This paper focuses on bundled carbon nanotubes and their different spatial arrangements viz. single wall CNTs (SWCNTs), multiwall CNTs (MWCNTs) and mixed CNT bundles (MCBs). Such bundle configurations boost the performance of system in terms of reducing system latency and power consumption in addition providing system reliability. The significant novel contribution of this paper lies in executing eye-diagram analysis of the futuristic bundled CNT structures as interconnects. Eye-diagram is an important tool for analysing signal integrity effects. The several performance analyses have been performed in SPICE and ADS EDA tools at 22 nm technology node.

Ferroelectric Tunnel Junction Based Crossbar Array Design for Neuro-Inspired Computing

Ferroelectric tunnel junction (FTJ) based crossbar array is a promising candidate for the implementation of low-power and area-efficient neuro-inspired computing. In this paper, we fabricated and measured a 10 nm thick Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FTJ with > 100 on/off ratio and multi-state storage. We found out that the current density of this FTJ is too low for sensing circuitry to distinguish reliably and efficiently. To overcome the low current of FTJs, we suggested using an ultra-thin 1 nm FTJ and employing the concept of stacked capacitors from modern DRAM processes. Following this idea, we further projected a 1 nm thick stacked FTJ and ran the crossbar arrays in the 20 nm node, which shows a desirable summed current level on the order of 10 μA. To model a realistic data pattern of on-state and off-state devices in a 1024 × 1024 array, we mapped quantized weights from a fully connected layer of a deep neural network to the memory cells. The current accuracy and delay are evaluated using array-level SPICE simulations with the consideration of interconnect parasitics. The overall results suggest that FTJ crossbar array is of the potential for realizing neuro-inspired computing.

Efficient Parasitic-aware g m / I D - based Hybrid Sizing Methodology for Analog and RF Integrated Circuits

As the primary second-order effect, parasitic issues have to be seriously addressed when synthesizing high-performance analog and RF integrated circuits (ICs). In this article, a two-phase hybrid sizing methodology for analog and RF ICs is proposed to take into account parasitic effect in the early design stage. It involves symbolic modeling and mixed-integer nonlinear programming (MINLP) in the first phase, and a many-objective evolutionary algorithm (many-OEA)-based sizing refiner in the second phase. With the aid of our proposed current density factor and piecewise curve fitting technique, the g m / I D concept, which is typically utilized to solve the analog circuit design problem, can provide theoretical support to our accurate symbolic modeling. Thus, the intrinsic and interconnect parasitics can be accurately considered in our work with moderate modeling effort. A variety of electrical, geometric, and parasitic (including parasitic mismatch) constraints can be conveniently integrated into our MINLP problem formulation. Moreover, numerical simulations are embedded into the many-OEA-based sizing phase, which is able to tackle floorplan co-optimization. With such dynamic floorplan variation, the parasitics accuracy can be sustained along the evolution. The experimental results demonstrate high efficacy of our proposed parasitic-aware hybrid sizing methodology.

RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars

Resistive crossbars designed with nonvolatile memory devices have emerged as promising building blocks for deep neural network (DNN) hardware, due to their ability to compactly and efficiently realize vector-matrix multiplication (VMM), the dominant computational kernel in DNNs. However, a key challenge with resistive crossbars is that they suffer from a range of device and circuit level nonidealities, such as driver resistance, sensing resistance, sneak paths, interconnect parasitics, nonlinearities in the peripheral circuits, stochastic write operations, and process variations. These nonidealities can lead to errors in VMMs, eventually degrading the DNN's accuracy. It is therefore critical to study the impact of crossbar nonidealities on the accuracy of large-scale DNNs (with millions of neurons and billions of synaptic connections). However, this is challenging because the existing device and circuit models are too slow to use in application-level evaluations. We present RxNN, a fast and accurate simulation framework to evaluate large-scale DNNs on resistive crossbar systems. RxNN splits and maps the computations involved in each DNN layer into crossbar operations, and evaluates them using a fast crossbar model (FCM) that accurately captures the errors arising due to crossbar nonidealities while being four-to-five orders of magnitude faster than circuit simulation. FCM models a crossbar-based VMM operation using three stages-nonlinear models for the input and output peripheral circuits (digital-to-analog and analog-to-digital converters), and an equivalent nonideal conductance matrix for the core crossbar array. We implement RxNN by extending the Caffe machine learning framework and use it to evaluate a suite of six large-scale DNNs developed for the ImageNet Challenge (ILSVRC). Our experiments reveal that resistive crossbar nonidealities can lead to significant accuracy degradations (9.6%-32%) for these large-scale DNNs. To the best of our knowledge, this article is the first quantitative evaluation of the accuracy of large-scale DNNs on resistive crossbar-based hardware. We also demonstrate that RxNN enables fast model-in-the-loop retraining of DNNs to partially mitigate the accuracy degradation.

Memristor-Based Analog Recursive Computation Circuit for Linear Programming Optimization

Linear programming optimization is central to engineering designs, logistics management, and decision-making in every sector of the economy. Traditional hardware using CPU and GPU platforms for this purpose is severely limited by the scaling of the transistor technology. In this article, we design an analog in-memory computation circuit for accelerating linear programming optimization problems. The scheme includes a memristive crossbar array and analog peripheral circuits that do not require DAC/ADC between each algorithm iteration. In addition, several key parameters related to nonideal device characteristics and interconnect parasitics are discussed for providing practical guidelines. Furthermore, three design schemes are proposed to alleviate the computation error caused by the interconnect resistance for a large-scale crossbar array implementation. Optimal design parameters are quantified under a given number of array size and memristive resistance. Finally, the proposed hardware accelerator and error mitigation techniques are applied to six real-world power system optimization problems. The results show that the average error of generator power and the overall cost is less than 3%. It is demonstrated that the proposed accelerator achieves area, delay, and energy consumption reductions of $\sim 151\times $ , $\sim 33\times $ , and $\sim 21\times $ , respectively, compared with the CMOS digital circuits at the 16-nm technology node for a $1000\times1000$ array with 6-bit precision.

Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.

A broadband small‐signal model extraction methodology over 0.2‐220 GHz for bulk FinFETs in RF CMOS technology

AbstractThis study presents a physical‐based broadband radio frequency (RF) small‐signal equivalent circuit model (ECM) for triple‐gate (TG) bulk fin field‐effect transistors (FinFETs) and its extraction methodology. To increase model accuracy and extend the effective frequency band, substrate effect, test ground‐signal‐ground (G‐S‐G) pads, and metal interconnection parasitics are considered together in the transistor model. All the elements in the model are extracted from a combination of analysis and physical equations using multibias scattering parameters. On the basis of the proposed model, the simulation results correspond to the measured results in the frequency range from 200 MHz to 220 GHz without any complex fitting or optimization steps.

Intrinsic Bounds for Computing Precision in Memristor-Based Vector-by-Matrix Multipliers

Analog computing with crossbars of memristors is a promising approach to build compact energy-efficient vector-by-matrix multiplier (VMM), a key block in many data-intensive algorithms. However, device non-linearity, process variations, interconnect parasitics, noise, and memory state drift limit the computing precision of such systems. In this article, we investigate the impact of such non-idealities in analog current-mode memristive VMMs through simulations and experiments on the most prospective passive crossbars. We show that there is an optimal tuning voltage to minimize the computation error. Furthermore, error balancing and bootstrapping are introduced as two techniques for improving the precision. It is also shown that when size of N × N crossbar is scaled up, the optimum interconnect wire conductance should increase quadratically with N to preserve the computing precision when using naive error balancing approach, and that the differential scheme is imperative for temperature insensitive operation and also to reduce the IR-drop effect.

A Prominent Approach to Design Low Noise Amplifiers for 802.11 Wireless Receiver Frontends

With the efforts of innovative consortium, wireless local area network (WLAN) became alternative standard in wireless local area networking applications. From the beginning the data rate keeps pace from mega bits per second (Mbps) up to giga bits per second. The ease of adaptability of WLAN protocol and the need for high data rate communication system made a reason to develop a solution and to incorporate real time wireless transceivers on network interface cards and FPGAs. Over the past decade, the RFIC technology became the hive of communication industry, with the proliferation of 802.11 a, g, n, ac, ad wireless protocols. The applications like ultra wide band (UWB), digital TV broadcasting and global positioning system found their way to main-stream gadgets. With the design preferences such as interconnect parasitics, interconnects and coupling between devices the passive elements must be precisely designed. In this article, novel requirements of low noise amplifier (LNA) design for 2.4 GHz application with noise modelling is presented.

Electromigration- and Parasitic-Aware ILP-Based Analog Router

Interconnect and via failures due to the electromigration (EM) effect have become increasingly challenging in the advanced technology as a result of shrinking feature size. The parasitic effect, which has to be normally represented as analog and radio frequency (RF) circuit constraints for effective suppression in practice, has also made the modern physical design more intractable. In this paper, we present a new integer-linear-programming-based EM-aware and sensitivity-aware analog/RF router, which can effectively address the EM constraints as well as interconnect parasitics and matching constraints along the routing paths. Interconnect parasitics can be evaluated in the sensitivity analysis so that an appropriate width can be adopted for each subnet in order to gain better circuit performance. Any mismatch can be also minimized between ideally matching nets whenever the primitive methods fail to find exactly matched routes for these sensitive nets. By using our proposed routing methodology, the EM constraints are taken into account to guarantee a final EM-compliant routing solution. The experimental results show that our proposed method is able to produce better circuit performance compared to the previous works while EM can be seriously addressed for analog/RF circuits.