Abstract
This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.
Highlights
H IGH energy and delay overheads for transferring data between processing and memory units have motivated intense interest in reducing the distance between memory and computation units
An electrical model of the current path is shown in Fig. 2; the bias voltage is applied between bit select lines (BSLs) 1 and 10, and in each row, the current path goes through input and output MTJs, two access transistors, and a segment of logic line (LL)
We have presented a methodology based on actual layout considerations for analyzing the parasitic effects in STTCRAM
Summary
H IGH energy and delay overheads for transferring data between processing and memory units have motivated intense interest in reducing the distance between memory and computation units. Different logic functions can be realized in the STT-CRAM by altering two parameters [1], [2], [8]: 1) the bias voltage (Vb) applied to the BSLs of the input MTJs and 2) the output preset state. An electrical model of the current path is shown in Fig. 2; the bias voltage is applied between BSLs 1 and 10, and in each row, the current path goes through input and output MTJs, two access transistors, and a segment of LL. The maximum allowable voltage drop is the difference between the maximum and minimum Vb, i.e., 226 mV in today’s CRAM and 51 mV in advanced CRAM for BUFFER, and a calculated value from Table 1 for any other gate. Wire parasitics do not impact the delay but only the IR drop
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